Achronix Speedster22i User Macro Guide - Manual (Page 32)

I/O Cells IPAD_D
Speedster Macro Cell Library www.achronix.com PAGE 15
IPAD_D
Registered Input Pad with Asynchronous or Synchronous Set/Reset
q
ce
d
rstn
dout
pad
clk
data_en
rstn
IPAD_D
Figure 1-7: IPAD_D Logic Symbol
IPAD_D is a registered input pad. Driving rstn low performs either a synchronous or
asynchronous reset of the input register as determined by the value of the rstmode parameter.
Upon assertion of the rstn signal, the input register is initialized to the value determined by
the rstvalue parameter.
Table 1-17: Ports
Name Type Description
pad Device pad.
rstn
Reset input. The active-low rstn input performs either a synchronous or
asynchronous set/reset operation as determined by the rstmode parame-
ter. The value that is initialized into the register is determined by the value
of the rstvalue parameter.
data_en
Input Register Clock Enable. A high value on data_en enables the Input
Register to clock the value on pad into the Input Register at the next rising
edge of clk. A low value on data_en allows the Input Register to retain its
current value.
dout
Positive-edge based data output. Data is clocked from the pad to dout
on the rising edge of clk.
clk Clock.
Table 1-18: Parameters
Parameter Defined Values Default Value
location
iostandard “LVCMOS18”
rstmode
rstvalue
keepmode
hysteresis
pvt_comp “none”, “own” “none”
odt “off”, “on” “off”
termination “50”, “60”, “75”, “100”, “120”, “240” “50”
input
input
input
output
input
“<pad_location>” ““
See Table 1‐1
“sync”, “async” “async”
“low”, “high” “low”
"pullup", "pulldown", "none" “none”
"none", "schmitt" “none”