Achronix Speedster22i User Macro Guide - Manual (Page 67)

Registers DFFE
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 51
DFFE
Positive Clock Edge D-Type Register with Clock Enable
ce
d
ck
DFFE
q
Figure 2-2: Logic Symbol
DFFE is a single D‐type register with data input (d), clock enable (ce), and clock (ck) inputs
and data (q) output. The data output is set to the value on the data input upon the next rising
edge of the clock if the active‐high clock enable input is asserted.
Pins
Table 2-4: Pin Descriptions
Name Type Description
d Data input.
ce Active-high clock enable input.
ck Positive-edge clock input.
q
Data output. The value present on the data input is transferred to the q out-
put upon the rising edge of the clock if the clock enable input is high.
Parameters
Table 2-5: Parameters
Parameter Defined Values Default Value
init 1’b0
init
The init parameter defines the initial value of the output of the DFFE register. This is the value
the register takes upon the initial application of power to the FPGA. The default value of the
init parameter is 1’b0.
Table 2-6: Function Table
Inputs Output
ce d ck q


input
input
input
output
1’b0, 1’b1
0 X X Hold
1 0 0
1 1 1