Achronix Speedster22i User Macro Guide - Manual (Page 141)

Memories BRAM80KFIFO
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 124
Table 6-21: Valid Read Width Versus Write Width Combinations per port for n x 5 width modes
Port Read
Width
Port Write Width
2kx40 4kx20 8kx10 16kx5 Other
40
20
10
5
Table 6-22: Valid Read Width Versus Write Width Combinations per port for n x 9 width modes
Port Read
Width
Port Write Width
2kx36 4kx18 8kx9 Other
36
18
9
Table 6-23: Valid Read Width Versus Write Width Combinations per port for 2
n
width modes
Port Read
Width
Port Write Width
2kx32 4kx16 8kx8 16kx4 32kx2 64kx1 Other
32
16
8
4
2
1
fwft
The fwft parameter defines if the FIFO is in the First‐Word‐Fall_Through mode. When the
fwft parameter is set to 1’b1, the first value written into the FIFO appears at the dout (and
doutp, doutxp if applicable) output without having to perform a read operation. If the fwft
parmaeter is set to 1’b0, the first data word written into the FIFO is available at the FIFO
output one rdclk clock cycle after the first read operation. This parameter only effects the
availability of the first word written into the FIFO after an empty condition. Operation of the
two modes is the same after the first read operation is performed. The default value of the fwft
parmeter is 1’b0. Note that the fwft parameter may only be set to 1’b1 when the sync_mode
parameter is set to 1’b0.
en_out_reg
The en_out_reg parameter enables the register at the output of the FIFO. A value of 1’b0
disables the output register. When the output register is enabled by setting the en_out_reg to
1’b1, there is an additional cycle of latency for each read operation. The en_out_reg parameter
is only set to its non‐default value when the FIFO is in single clock mode (sync_mode = 1’b1).
When the FIFO is in dual clock mode, the en_out_reg parameter must be set to 1’b1. The
default value of the en_out_reg parameter is 1’b1.
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