Achronix Speedster22i User Macro Guide - Manual (Page 57)

I/O Cells OPAD_DIFFD2
Speedster Macro Cell Library www.achronix.com PAGE 40
OPAD_DIFFD2
DDR Differenctial Output Pad with Asynchronous or Synchronous
Set/Reset
q
ce
d
rstn
pad
OPAD_DIFFD2
q
ce
d
rstn
q d
rstn
q d
rstn
rstn
dina
dinb
data_en
clk
padn
Figure 1-20: OPAD_DIFFD2 Logic Symbol
OPAD_DIFFD2 is a Double Data Rate (DDR) differential output pad with active‐high
registered output enable. There is an additional stage of registers on the outputs to allow the
logic level on the pad to changes on both the rising and falling edges of the clock, but allow
the interface signals from the FPGA core to change on the rising edge of the clock. This
additional level of registers provides a full cycle to get into and out of the FPGA core.
Table 1-46: Ports
Name Type Description
pad Device output pad.
padn Device complement output pad.
dina
Positive-edge based data input. Data is clocked into the dina register upon
the rising edge of the txclk input when the txdata_en signal is high. It is
routed to the pad on the following rising edge of the clock. If the oe input
was high during the same clock period of the dina input, the pad will be
actively driven with the dina data during the portion of the clock period
when txclk is high.
dinb
Negative-edge based data input. Data is clocked into the dinb register
upon the falling edge of the txclk input when the txdata_en signal is high. It
is routed to the pad on the following rising edge of the clock. If the oe input
was high during the same clock period of the dinb input, the pad will be
actively driven with the dinb data during the portion of the clock period
when txclk is low.
data_en
Transmit Data Enable (active-high). A high value on data_en enables the
dina and dinb inputs to be clocked into the transmit registers.
rstn
Asynchronous Reset input. A low value on rstn performs an asynchronous
initialization of the Output Register if the rstmode parameter is set to “async”.
The value initialized into the Output Register is determined by the value of
the rstvalue parameter.
clk Clock Input.
output
output
input
input
input
input
input