Achronix Speedster22i User Macro Guide - Manual (Page 120)

Memories BRAM80K
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 103
BRAM80K Verilog Instantiation Template
BRAM80K #(
.porta_read_width(40),
.porta_write_width(40),
.porta_write_mode("write_first"),
.porta_clock_polarity("rise"),
.porta_en_out_reg(1'b0),
.porta_regce_priority("rstreg"),
.porta_peval(1'b1),
.porta_reg_rstval(1'b1),
.porta_latch_rstval(1'b1),
.porta_initval(40'h0),
.porta_srval(40'h0),
.portb_read_width(40),
.portb_write_width(40),
.portb_write_mode("write_first"),
.portb_clock_polarity("rise"),
.portb_en_out_reg(1'b0),
.portb_regce_priority("rstreg"),
.portb_peval(1'b1),
.portb_reg_rstval(1'b1),
.portb_latch_rstval(1'b1),
.portb_initval(40'h0),
.portb_srval(40'h0),
.mem_init_file(""),
.initd_000(256'h0),
.initd_001(256'h0),
.initd_002(256'h0),
.initd_003(256'h0),
.initd_004(256'h0),
.initd_005(256'h0),
.initd_006(256'h0),
.initd_007(256'h0),
.initd_008(256'h0),
.initd_009(256'h0),
.initd_010(256'h0),
.initd_011(256'h0),
.initd_012(256'h0),
.initd_013(256'h0),
.initd_014(256'h0),
.initd_015(256'h0),
.initd_016(256'h0),
.initd_017(256'h0),
.initd_018(256'h0),