Heading3 - verilog instantiation template, Heading3 - vhdl instantiation template, Verilog instantiation template – Achronix Speedster22i User Macro Guide User Manual
Page 24: Vhdl instantiation template
I/O Cells
IOPAD_D
Speedster Macro Cell Library
PAGE 7
Verilog Instantiation Template
IOPAD_D #(.location(""),
.iostandard("LVCMOS18"),
.drive("16"),
.txregmode("reg"),
.rxregmode("reg"),
.oeregmode("reg"),
.rstmode("async"),
.rstvalue("low"),
.slew("slow"),
.keepmode("none"),
.hysteresis("none"),
.open_drain("false"),
.pvt_comp("none"),
.termination("50"),
.odt("off"))
instance_name (.pad(user_pad), .din(user_din), .dout(user_dout),
.oe(user_oe), .txdata_en(user_txdata_en), .rxdata_en(user_rxdata_en),
.txrstn(user_txrstn), .rxrstn(user_rxrstn), .oerstn(user_rxrxtn),
.srstn(user_txsrstn), ..txclk(user_txclk), .rxclk(user_rxclk),
.oeclk(user_oeclk));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------