Achronix Speedster22i User Macro Guide - Manual (Page 161)

Memories BRAM80KFIFO
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 144
Reading from an Almost Empty FIFO (en_rd_when_empty = 1’b0, fwft = 1’b0)
Figure 6-18: Reading From an Almost Empty FIFO (en_rd_when_empty = 1’b0, fwft = 1’b0)
wrclk
rdclk
wren
rden
dout
almost_empty
read_err
1. Almost Empty Offset programmed for 6 40-bit words (aempty_offset = 17’h00005)
Note: This timing diagram assumes:
2. wptr_sync_stages = 2’b00
3. en_rd_when_empty = 1’b0
wrd 5
empty
A B C D
A Event : Finish writing 6 words to the FIFO.
Event : The almost_empty flag is deasserted one wrclk plus (wrptr_sync_stages + 3) B
din
wrd 0 wrd 1
wrd 4
wrd 2 wrd 3 wrd 4 wrd 5
4. fwft = 1’b0
E F G
rdclk active clock edges after the sixth (wrd 5) word is presented at the din input
with wren high.
Event : Begin to read the six word from the FIFO. C
Event : The almost_empty flag is asserted the cyle after the first read request, when D
five words remain in the FIFO.
Event : The empty flag is asserted after the last (sixth) word is read from the FIFO. E
The rden signal remains high, attempting to read an empty FIFO.
Event : The read_err signal is asserted the cycle after the attempt to read an empty FIFO.
F
The sixth (wrd 5) word remains at the dout output.