Achronix Speedster22i User Macro Guide - Manual (Page 177)

Memories LRAMFIFO
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 160
LRAMFIFO
LRAM-Based 64-Word FIFO Memory
LRAMFIFO
dout[width - 1:0]
full
read_err
din[width - 1:0]
rstn
wren
rden
empty
almost_empty
almost_full
write_err
wrclk
rdclk
Figure 6-31: Logic Symbol
The LRAMFIFO implements a 64 word by n‐bit FIFO memory block utilizing the embedded
LRAM blocks and LUTs. The LRAMFIFO can be configured to support a variety of widths in
increments of one bit. The read and write clocks may be either synchronous or asynchronous
with respect to each other. If the user read and write clocks are the same clock, the user may
set the sync_mode to 1’b1 to enable faster and synchronous generation of the status flags.
Figure 6-32: LRAMFIFO Block Diagram
LRAM
Output
dout
Memory Write
Pointer
Logic Read
Pointer
Logic
Memory Control /
Flag Generation
Logic
din
Register
wren
wrclk
rstn
rdclk
full
empty
almost_full
almost_empty
write_err
read_err
rden