Table - table 4-3: function table, Heading3 - verilog instantiation template, Heading3 - vhdl instantiation template – Achronix Speedster22i User Macro Guide User Manual
Page 102: Table, 4‐3: function table
Lookup Table (LUT) Functions
LUT4
Speedster Macro Cell Library
PAGE 85
Table 4-3: Function Table
din3
din2
din1
din0
q
0
0
0
0
lut_function[0]
0
0
0
1
lut_function[1]
0
0
1
0
lut_function[2]
0
0
1
1
lut_function[3]
0
1
0
0
lut_function[4]
0
1
0
1
lut_function[5]
0
1
1
0
lut_function[6]
0
1
1
1
lut_function[7]
1
0
0
0
lut_function[8]
1
0
0
1
lut_function[9]
1
0
1
0
lut_function[10]
1
0
1
1
lut_function[11]
1
1
0
0
lut_function[12]
1
1
0
1
lut_function[13]
1
1
1
0
lut_function[14]
1
1
1
1
lut_function[15]
Verilog Instantiation Template
LUT4 #(.lut_function(16’h0123))
instance_name(.dout(user_out),
.din0(user_in0),
.din1(user_in1),
.din2(user_in2),
.din3(user_in3));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
LUT4_instance_name : LUT4
generic map (lut_function => X”0123”)
port map (dout => user_out,
din0 => user_din0,
din1 => user_din1,
din2 => user_din2,
din3 => user_din3);