Table - table 6-15: bram80kfifo pin description – Achronix Speedster22i User Macro Guide User Manual

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BRAM80KFIFO

Speedster22i Macro Cell Library

Achronix Semiconductor Proprietary

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Table 6-15: BRAM80KFIFO Pin Description

Name

Type

Clock

Domain

Description

din[31:0]

Write port data input.

dinp[3:0]

Write port parity input (may be used for data).

dinpx[3:0]

Write port extended parity input (may be used for data).

wren

Write enable (active-high). Data is written into the FIFO at the next
active edge of the write clock when wren is driven high, as long as the
full flag is not asserted.

wrrst

Write port FIFO reset (programmable, default active-high). Asserting
the wrrst signal resets the FIFO to clear both the read and the write
pointers and set the FIFO to the empty condition. The contents of the
FIFO are not affected by the wrrst signal.

wrclk

Write clock. (rising edge).

rden

Read enable (active-high). Data is read from the FIFO at the next
active edge of the clock when the rden is driven high, as long as the
empty flag is not asserted.

rdrst

Read port FIFO reset (programmable, default active-high). Asserting
the rdrst signal resets the FIFO to clear both the read and the write
pointers and set the FIFO to the empty condition. The contents of the
FIFO are not affected by the rdrst signal.

rdclk

Read clock (rising edge).

outregce

Output register clock enable (active-high).

rstreg

Output register reset (programmable, default active-high).

dout[31:0]

Read port dout output.

doutp[3:0]

Read port parity output (used for data).

doutpx[3:0]

Read port extended parity output (used for data).

empty

Empty flag (active-high).

full

Full flag (active-high).

almost_empty

Almost Empty flag (active-high).

almost_full

Almost Full flag (active-high).

write_err

Write Error flag (active-high).

read_err

Read Error flag (active-high).

wrcount[16:0]

FIFO write pointer.

rdcount[16:0]

FIFO read pointer.

input

wrclk

input

wrclk

input

wrclk

input

wrclk

input

prog.

input

wrclk

input

rdclk

input

prog.

input

rdclk

input

rdclk

input

rdclk

output

rdclk

output

rdclk

output

rdclk

output

rdclk

output

wrclk

output

rdclk

output

wrclk

output

wrclk

output

rdclk

output

prog.

output

prog.

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