Achronix Speedster22i User Macro Guide - Manual (Page 110)

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Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 93
porta_reg_rstval(portb_reg_rstval)
The porta_reg_rstval(portb_reg_rstval) parameter defines the active level of the Port A(B)
output register reset input. Assigning a value of 1’b0 to porta_reg_rstval(portb_reg_rstval)
configures the Port A(B) output register to have an active‐low synchronous reset, while
assigning a value of 1’b1 configures the Port A(B) output register to have an active‐high
synchronous reset. The default value of the porta_reg_rstval(portb_reg_rstval) parameter is
1’b1.
porta_regce_priority(portb_regce_priority)
The porta_regce_priority(portb_regce_priority) parameter defines the priority of the
outregcea(outregceb) clock enable input relative to the rstrega(rstregb) reset input during an
assertion of the rstrega(rstregb) signal on the output register of Port A(B). Setting
porta_regce_priority(portb_regce_priority) to “rstreg” allows the Port A(B) output register to
be set/reset at the next active edge of the Port A(B) clock without requiring a specific value on
the outregcea (outregceb) output register clock enable input. Setting porta_regce_priority
(portb_regce_priority) to “regce” requires that the outregcea(outregceb) output register clock
enable input is high for the output register set/reset operation to occur at the next active edge
of the Port A(B) clock.
porta_initval(portb_initval)
The porta_initval(portb_initval) parameter defines the power‐up default value of the data on
the output of Port A(B) latch(register if porta_en_out_reg(portb_en_out_reg)=1’b1). The 40‐bit
porta_initval(portb_initval) parameter assignment is dependent on the porta_read_width
(portb_read_width). The association of the of the porta_initval(portb_initval) parameter
values to the douta,doutpa,doutpxa (doutb,doutpb,doutpxb) bits is assigned according to
Table 6‐3: Relationship of porta_initval(portb_initval) bit positions to
douta,doutpa,doutpxa (doutb,doutpb,doutpxb) . The default value of
porta_initval(portb_initval) is 40’h0.
Table 6-3: Relationship of porta_initval(portb_initval) bit positions to douta,doutpa,doutpxa
(doutb,doutpb,doutpxb)
porta_read_width
(portb_read_width)
doutpxa (doutpxb)
porta_initval[39:36]
(portb_initval[39:36])
doutpa (doutpb)
porta_initval[35:32]
(portb_initval[35:32])
douta (doutb)
porta_initval[31:0]
(portb_initval[31:0])
40 porta_initval[39:36] porta_initval[35:32] porta_initval[31:0]
36 4’hx porta_initval[35:32] porta_initval[31:0]
32 4’hx 4’hx porta_initval[31:0]
20 2’bxx,porta_initval[19:18] 2’bxx,porta_initval[17:16] 16’hxxxx,porta_initval[15:0]
18 4’hx 2’bxx,porta_initval[17:16] 16’hxxxx,porta_initval[15:0]
16 4’hx 4’hx 16’hxxxx,porta_initval[15:0]
10 3’bxxx,porta_initval[9] 3’bxxx,porta_initval[8] 24’hxxxxxx,porta_initval[7:0]
9 4’hx 3’bxxx,porta_initval[8] 24’hxxxxxx,porta_initval[7:0]
8 4’hx 4’hx 24’hxxxxxx,porta_initval[7:0]
5 4’hx 3’bxxx,porta_initval[4] 28’hxxxxxxx,porta_initval[3:0]
4 4’hx 4’hx 28’hxxxxxxx,porta_initval[3:0]
2 4’hx 4’hx 30’hxxxxxxxx,porta_initval[1:
0]
1 4’hx 4’hx 31’hxxxxxxxx,porta_initval[0]