Achronix Speedster22i User Macro Guide - Manual (Page 157)

Memories BRAM80KFIFO
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 140
Figure 6‐9: Read and Write Pointer Reset Input Selection Block Diagram shows the block
diagram of the FIFO Reset Selection circuitry. The circuits to configure the Read Pointer and
Write Pointer resets are identical. The wrrst_sync_stages(rdrst_sync_stages) parameter
configures the depth of the wrrst(rdrst) synchronizer from two to five stages according to the
definitions in
Table 6‐28: Mapping wrrst_sync_stages Parameter Settings to Synchro‐
nization Stage Depth .( Table 6‐31: Mapping rdrst_sync_stages Parameter Settings to
Synchronization Stage Depth ). The wrrst_sync_stages(rdrst_sync_stages) parameter allows
the user the capability to tune the synchronizer as a function of frequency. A higher value of
the wrrst_sync_stages(rdrst_sync_stages) parameter setting is recommended for higher
frequencies of FIFO operation while lower settings may be used for lower frequencies. Note
that higher settings increase the number of cycles that the wrrst(rdrst) have to be asserted and
increase the number of cycles between the deassertion of the wrrst(rdrst) input and the time
that the user may begin to write(read) the FIFO.
For reliable operation, the user should not attempt to read or write the FIFO during a reset
operation. If the wrrst synchronizer is used, the wrrst reset should be active for at least
wrrst_sync_stages +3 rdclk cycles and if the rdrst synchronizer is used, the rdrst reset should
be active for at least rdrst_sync_stages + 3 rdclk cycles. Write operations should not begin
before wrrst_sync_stages + 3 rdclk cycles after the wrrst signal is inactive AND
rdrst_sync_stages + 3 rdclk cycles after the rdrst signal is inactive to allow the deassertion of
the resets to reach their synchronized clock domains.
The highest reset performance is achieved with a synchronous (single clock) FIFO. For an
asynchronous FIFO, the highest reset performance is achieved by using a reset input that is
synchronous with respect to the write clock domain. The Write Pointer should be configured
with a synchronous reset input(wrrst_sync_mode = 2’b00) and the Read Pointer should be
configure to be reset by the synchronized wrrst input(rdrst_sync_mode = 2’b11). The user
should then connect the wrrst input to the FIFO reset signal. The user should tie the unused
reset input to its inactive logic level.