Motorola ColdFire MCF5281 - Manual (Page 160)

System Control Module (SCM)
8-8 Freescale Semiconductor
Figure 8-6. Arbiter Module Functions
8.5.1 Overview
The basic functionality is that of a 4-port, pipelined internal bus arbitration module with the following
attributes:
• The master pointed to by the current arbitration pointer may get on the bus with zero latency if the
address phase is available. All other requesters face at least a one cycle arbitration pipeline delay
in order to meet bus timing constraints on address phase hold.
• If a requester will get an immediate address phase (that is, it is pointed to by the current arbitration
pointer and the bus address phase is available), it will be the current bus master and is ignored by
arbitration. All remaining requesting ports are evaluated by the arbitration algorithm to determine
the next-state arbitration pointer.
• There are two arbitration algorithms, fixed and round-robin. Fixed arbitration sets the next-state
arbitration pointer to the highest priority requester. Round-robin arbitration sets the next-state
arbitration pointer to the highest priority requester (calculated by adding a requester's fixed priority
to the current bus master’s fixed priority and then taking this sum modulo the number of possible
bus masters).
• The default priority is FEC (M3) > DMA (M2) > internal master (M1) > CPU (M0), where M3 is
the highest and M0 the lowest priority. M3 is not used for the MCF5216 and MCF5214.
• There are two actions for an idle arbitration cycle, either leave the current arbitration pointer as is
or set it to the lowest priority requester.
• The anti-lock-out logic for the fixed priority scheme forces the arbitration algorithm to round-robin
if any requester has been held for longer than a specified cycle count.
SRAM1
MPARK RAMBAR
CPU
M0
DMA
M2
Internal
M1
Bus
Master
FEC
M3
EIM
Internal
MARB
Modules
SDRAMC
“back door” to SRAM and Flash
*Not used on
MCF5214/16
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3