Motorola ColdFire MCF5281 - Manual (Page 571)

Queued Analog-to-Digital Converter (QADC)
Freescale Semiconductor 28-33
Figure 28-20. Conversion Timing
If the amplifier bypass mode is enabled for a conversion by setting the amplifier bypass (BYP) field in the
CCW, the timing changes to that shown in
Figure 28-21 . See Section 28.6.7, “Conversion Command Word
Table (CCW) for more information on the BYP field. The initial sample time is eliminated, reducing the
potential conversion time by two QCLKs. When using the bypass mode, the external circuit should be of
low source impedance (typically less than 10 k
Ω). Also, the loading effects on the external circuitry of the
QADC need to be considered, because the benefits of the sample amplifier are not present.
NOTE
Because of internal RC time constants, use of a two QCLK sample time in
bypass mode will cause serious errors when operating the QADC at high
frequencies.
Figure 28-21. Bypass Mode Conversion Timing
28.7.3.3 Channel Decode and Multiplexer
The internal multiplexer selects one of the eight analog input signals for conversion. The selected input is
connected to the sample buffer amplifier or to the sample capacitor. The multiplexer also includes positive
and negative stress protection circuitry, which prevents deselected channels from affecting the selected
channel when current is injected into the deselected channels.
28.7.3.4 Sample Buffer
The sample buffer is used to raise the effective input impedance of the A/D converter, so that external
factors (higher bandwidth or higher impedance) are less critical to accuracy. The input voltage is buffered
onto the sample capacitor to reduce crosstalk between channels.
28.7.3.5 Comparator
The comparator output feeds into the SAR, which accumulates the A/D conversion result sequentially,
beginning with the MSB.
Sample Time Successive Approximation Resolution Sequence
QCLK
Buffer
Sample
Time:
2 Cycles
Final
Sample
Time:
n Cycles
(2,4,8,16)
Resolution
Time:
10 Cycles
Sample Time Successive Approximation Resolution Sequence
QCLK
Sample
Time:
n CYCLES
(2,4,8,16)
Resolution
Time:
10 Cycles
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3