8 flexcan error and status register (estat), 8 flexcan error and status register (estat) -25 – Motorola ColdFire MCF5281 User Manual
Page 495
FlexCAN
Freescale Semiconductor
25-25
25.5.8
FlexCAN Error and Status Register (ESTAT)
ESTAT reflects various error conditions, some general status of the device, and is the source of three
interrupts to the host. The reported error conditions (bits 15:10) are those occurred since the last time the
host read this register. The read action clears these bits to 0.
All the bits in this register are read only, except for BOFF_INT, WAKE_INT and ERR_INT, which are
interrupt sources and can be written by the host to ‘1’.
31
21
20
19
18
17
16
Field
MID[28:18]
—
MID[17:15]
Reset
1111_1111_1110_1111
R/W
R/W
15
1
0
Field
MID[14:0]
—
Reset
1111_1111_1111_1110
R/W
R/W
Address
IPSBAR + 0x1C_0010 (RXGMASK), 0x1C_0014 (RX14MASK), 0x1C_0018 (RX15MASK)
Figure 25-12. Rx Mask Registers (RXGMASK, RX14MASK, and RX15MASK)
Table 25-16. RXGMASK, RX14MASK, and RX15MASK Field Descriptions
Bits
Name
Description
31–21
MID
Mask ID. MID[28:18] are used to mask standard or extended format frames.
0 corresponding incoming ID bit is “don’t care”.
1 corresponding ID bit is checked against the incoming ID bit, to see if a match exists.
20
—
Reserved. The IDE bit of a received frame is always compared. Its location in the mask (bit 19) is
always 1, regardless of any CPU write to this bit.
19
—
Reserved. The RTR/SRR bit of a received frame is never compared to the corresponding bit in the
MB ID field. Note, however, that remote request frames (RTR = 1) are never received into MBs. RTR
mask bits locations in the mask (bits 20 and 0) are always read as ’0’, regardless of any CPU write
to these bits.
18–1
MID
Mask ID. MID[17:0] are only used to mask extended format frames.
0 corresponding incoming ID bit is “don’t care”.
1 corresponding ID bit is checked against the incoming ID bit, to see if a match exists.
0
—
Reserved. The RTR/SRR bit of a received frame is never compared to the corresponding bit in the
MB ID field. Note, however, that remote request frames (RTR = 1) are never received into MBs. RTR
mask bits locations in the mask (bits 20 and 0) are always read as ’0’, regardless of any CPU write
to these bits.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3