Motorola ColdFire MCF5281 - Manual (Page 579)

Queued Analog-to-Digital Converter (QADC)
Freescale Semiconductor 28-41
.
Figure 28-29. CCW Priority Situation 7
Situations S8 and S9 ( Figure 28-30 and Figure 28-31 ) repeat the same two situations with the RESUME
bit set to a 1. When the RESUME bit is set, following suspension, queue 2 resumes execution with the
aborted CCW, not the first CCW, in the queue.
Figure 28-30. CCW Priority Situation 8
T1
PAUSE Q1:
Q2:
QS:
IDLE ACTIVE
IDLE ACTIVE IDLE
0010 0110 1010 0010
ACTIVE
0000
IDLE
Q1:
PF1
C1 C2
0000 1010
ACTIVE
0110
C1 Q2:
T2
C1
PF2
T1
C3 C4
CF1
C3
CF2
SUSPEND PAUSE SUSPEND
T2
C1 C3 C2
ACTIVE ACT
0101
C4
IDLE
Q1:
Q2:
QS:
IDLE
IDLE
0000 1000 0010
ACTIVE
C1 C2
T1
Q1:
C1
C3 C4
IDLE
Q2:
PF1
PAUSE
ACTIVE
CF1
T1
ACTIVE
SUSPEND
0100
ACTIVE
ACTIVE
0110 1010
C2 C3 C4
CF2
T2
0000
RESUME=1 C2
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3