Motorola ColdFire MCF5281 - Manual (Page 725)

Register Memory Map
Freescale Semiconductor A-13
IPSBAR + 0x1118 Upper 32 bits of individual hash table IAUR 32
IPSBAR + 0x111C Lower 32 bits of individual hash table IALR 32
IPSBAR + 0x1120 Upper 32-bits of group hash table GAUR 32
IPSBAR + 0x1124 Lower 32-bits of group hash table GALR 32
IPSBAR + 0x1144 Transmit FIFO Watermark TFWR 32
IPSBAR + 0x114C FIFO Receive Bound Register FRBR 32
IPSBAR + 0x1150 FIFO Receive Start Address FRSR 32
IPSBAR + 0x1180 Pointer to Receive Descriptor Ring ERDSR 32
IPSBAR + 0x1184 Pointer to Transmit Descriptor Ring ETDSR 32
IPSBAR + 0x1188 Maximum Receive Buffer Size EMRBR 32
IPSBAR +
0x1200-0x13FF
RAM used to store management counters MIB_RAM 32
GPIO Registers
IPSBAR +
0x10_0000
Port A Output Data Register PORTA 8
IPSBAR +
0x10_0001
Port B Output Data Register PORTB 8
IPSBAR +
0x10_0002
Port C Output Data Register PORTC 8
IPSBAR +
0x10_0003
Port D Output Data Register PORTD 8
IPSBAR +
0x10_0004
Port E Output Data Register PORTE 8
IPSBAR +
0x10_0005
Port F Output Data Register PORTF 8
IPSBAR +
0x10_0006
Port G Output Data Register PORTG 8
IPSBAR +
0x10_0007
Port H Output Data Register PORTH 8
IPSBAR +
0x10_0008
Port J Output Data Register PORTJ 8
IPSBAR +
0x10_0009
Port DD Output Data Register PORTDD 8
IPSBAR +
0x10_000A
Port EH Output Data Register
(Reserved for MCF5214 and MCF5216)
PORTEH 8
IPSBAR +
0x10_000B
Port EL Output Data Register PORTEL 8
Table A-3. Register Memory Map (continued)
Address Name Mnemonic Size
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3