Motorola ColdFire MCF5281 - Manual (Page 398)

DMA Timers (DTIM0–DTIM3)
21-6 Freescale Semiconductor
IPSBAR
Offset:
0x 00_04 03 (DTER0)
0x 00_044 3 (DTER1)
0x 00_048 3 (DTER2)
0x 00_04C 3 (DTER3)
Access: User read/write
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 REF CAP
W w1c w1c
Reset: 0 0 0 0 0 0 0 0
Figure 21-4. DTERn Registers
Table 21-4. DTERn Field Descriptions
Field Description
7–2 Reserved, must be cleared.
1
REF
Output reference event. The counter value (DTCNn) equals DTRRn. Writing a 1 to REF clears the event condition.
Writing a 0 has no effect.
0
CAP
Capture event. The counter value has been latched into DTCRn. Writing a 1 to CAP clears the event condition.
Writing a 0 has no effect.
REF DTMRn[ORRI] DTXMRn[DMAEN]
0 X X No event
1 0 0 No request asserted
1 0 1 No request asserted
1 1 0 Interrupt request asserted
1 1 1 DMA request asserted
CAP DTMRn[CE]
DTXMRn
[DMAEN]
0 XX X No event
1 00 0 Disable capture event output
1 00 1 Disable capture event output
1 01 0 Capture on rising edge and trigger interrupt
1 01 1 Capture on rising edge and trigger DMA
1 10 0 Capture on falling edge and trigger interrupt
1 10 1 Capture on falling edge and trigger DMA
1 11 0 Capture on any edge and trigger interrupt
1 11 1 Capture on any edge and trigger DMA
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3