Motorola ColdFire MCF5281 - Manual (Page 752)

Index-4 Freescale Semiconductor
I
2
C input/output timing specifications 33-20
I
2
C output timing between SCL and SDA 33-20
JTAG and boundary scan timing 33-25
maximum ratings 33-1
MII async inputs signal timing 33-23
MII receive signal timing 33-21
MII serial management channel timing 33-23
MII transmit signal timing 33-22
PLL specifications 33-4
QADC absolute maximum ratings 33-8
QADC operating conversion specifications 33-10
QADC operating electrical specifications 33-9
QSPI AC timing specifications 33-24
QSPI specifications 33-24
reset and configuration override timing 33-19
SDRAM timing 33-17
thermal 33-2
EMAC
data representation 3-14
instructions
execution timing 3-13
summary 3-12
memory map 3-3
opcodes 3-14
operation
fractional 3-10
registers
BDM accesses 30-33
mask (MASK) 3-5
status (MACSR) 3-3
ENABLE_TEST_CTRL instruction 31-8
End-of-frame (EOF) 25-12
EPORT
low-power modes 7-10 , 11-1
memory map 11-3
overview 11-1
programming model 7-1
registers
data direction (EPDDR) 11-4
flag (EPFR) 11-6
pin assignment (EPPAR) 11-3
pin data (EPPDR) 11-6
port data (EPDR) 11-5
port interrupt enable (EPIER) 11-5
Error counters 25-13
Error interrupt (ERRINT) bit 25-27
Ethernet
address recognition 17-35
block diagram 17-2
buffer descriptors
receive (RxBD) 17-27
transmit (TxBD) 17-29
collision handling 17-42
electrical characteristics
MII receive signal timing 33-21
MII serial management channel timing 33-23
MII transmit signal timing 33-22
errors
handling 17-42
reception
CRC 17-44
frame length 17-44
non-octet 17-43
overrun 17-43
truncation 17-44
transmission
attempts limit expired 17-43
heartbeat 17-43
late collision 17-43
underrun 17-43
frame reception 17-35
frame transmission 17-33
hash table 17-38
initialization 17-30
operation
10 Mbps 7-Wire 17-4 , 17-32
10 Mbps and 100 Mbps MII 17-32
full duplex 17-4
, 17-41
half duplex 17-4
loopback 17-42
low-power modes 7-9
registers
control (ECR) 17-12
descriptor group upper/lower address
(GAUR/GALR) 17-21
descriptor individual upper/lower (IAUR/IALR) 17-20
descriptor individual upper/lower address
(IAUR/IALR) 17-20
FIFO receive bound (FRBR) 17-22
FIFO receive start (FRSR) 17-23
FIFO transmit FIFO watermark (TFWR) 17-22
interrupt event (EIR) 17-9
interrupt mask (EIMR) 17-10
MIB control (MIBC) 17-16
MII management frame (MMFR) 17-13
MII speed control (MSCR) 17-15
opcode/pause duration (OPD) 17-19
physical address low (PALRn) 17-18
physical address low/high (PALR, PAUR) 17-18
receive buffer size (EMRBR) 17-24
receive control (RCR) 17-16
receive descriptor active (RDAR) 17-11
receive descriptor ring start (ERDSR) 17-23
transmit buffer descriptor ring start (ETSDR) 17-24
transmit control (TCR) 17-17
transmit descriptor active (TDAR) 17-12
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3