Motorola ColdFire MCF5281 - Manual (Page 461)

I 2 C Interface
Freescale Semiconductor 24-7
24.3 Functional Description
The I
2
C module uses a serial data line (I2C_SDA) and a serial clock line (I2C_SCL) for data transfer. For
I
2
C compliance, all devices connected to these two signals must have open drain or open collector outputs.
The logic AND function is exercised on both lines with external pull-up resistors.
Out of reset, the I
2
C default state is as a slave receiver. Therefore, when not programmed to be a master or
responding to a slave transmit address, the I
2
C module should return to the default slave receiver state. See
Section 24.4.1, “Initialization Sequence,” for exceptions.
Normally, a standard communication is composed of four parts: START signal, slave address transmission,
data transfer, and STOP signal. These are discussed in the following sections.
24.3.1 START Signal
When no other device is bus master (I2C_SCL and I2C_SDA lines are at logic high), a device can initiate
communication by sending a START signal (see A in
Figure 24-7 ). A START signal is defined as a
high-to-low transition of I2C_SDA while I2C_SCL is high. This signal denotes the beginning of a data
transfer (each data transfer can be several bytes long) and awakens all slaves.
IPSBAR
Offset:
0x00_0310 (I2DR) Access: User read/write
7 6 5 4 3 2 1 0
R
DATA
W
Reset: 0 0 0 0 0 0 0 0
Figure 24-6. I
2
C Data I/O Register (I2DR)
Table 24-6. I2DR Field Description
Field Description
7–0
DATA
I
2
C data. When data is written to this register in master transmit mode, a data transfer is initiated. The most significant
bit is sent first. In master receive mode, reading this register initiates the reception of the next byte of data. In slave
mode, the same functions are available after an address match has occurred.
Note: In master transmit mode, the first byte of data written to I2DR following assertion of I2CR[MSTA] is used for
the address transfer and should comprise the calling address (in position D7–D1) concatenated with the
required R/W bit (in position D0). This bit (D0) is not automatically appended by the hardware, software must
provide the appropriate R/W bit.
Note: I2CR[MSTA] generates a start when a master does not already own the bus. I2CR[RSTA] generates a start
(restart) without the master first issuing a stop (i.e., the master already owns the bus). To start the read of data,
a dummy read to this register starts the read process from the slave. The next read of the I2DR register
contains the actual data.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3