Motorola ColdFire MCF5281 - Manual (Page 290)

Synchronous DRAM Controller Module
15-18 Freescale Semiconductor
15.2.4.1 Mode Register Settings
It is possible to configure the operation of SDRAMs, namely their burst operation and CAS latency,
through the SDRAM component’s mode register. CAS latency is a function of the speed of the SDRAM
and the bus clock of the DRAM controller. The DRAM controller operates at a CAS latency of 1, 2, or 3.
Although the DRAM controller supports bursting operations, it does not use the bursting features of the
SDRAMs. Because the processor can burst operand sizes of 1, 2, 4, or 16 bytes long, the concept of a fixed
burst length in the SDRAMs mode register becomes problematic. Therefore, the processor DRAM
controller generates the burst cycles rather than the SDRAM device. Because the processor generates a
new address and a
READ or WRITE command for each transfer within the burst, the SDRAM mode register
should be set either not to burst or to a burst length of one. This allows bursting to be controlled by the
processor.
The SDRAM mode register is written by setting the associated block’s DACR[IMRS]. First, the base
address and mask registers must be set to the appropriate configuration to allow the mode register to be
set. Note that improperly set DMR mask bits may prevent access to the mode register address. Thus, the
user should determine the mapping of the mode register address to the processor address bits to find out if
an access is blocked. If the DMR setting prohibits mode register access, the DMR should be reconfigured
to enable the access and then set to its necessary configuration after the
MRS command executes.
The associated CBM bits should also be initialized. After DACR[IMRS] is set, the next access to the
SDRAM address space generates the
MRS command to that SDRAM. The address of the access should be
selected to place the correct mode information on the SDRAM address pins. The address is not multiplexed
for the
MRS command. The MRS access can be a read or write. The important thing is that the address output
of that access needs the correct mode programming information on the correct address bits.
Figure 15-10 shows the MRS command, which occurs in the first clock of the bus cycle.
Figure 15-10. Mode Register Set ( MRS ) Command
15.3 SDRAM Example
This example interfaces a 512K x 32-bit x 4 bank SDRAM component to processor operating at 40 MHz.
Table 15-25 lists design specifications for this example.
A[23:0]
SRAS, SCAS
DRAMW
D[31:0]
MRS
SD_CS[1] or [0]
CLKOUT
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3