Motorola ColdFire MCF5281 - Manual (Page 746)

Revision History
B-10 Freescale Semiconductor
Section
17.4.6/Page 17-7
Add the following subsection entitled “Duplicate Frame Transmission”:
The FEC fetches transmit buffer descriptors (TxBDs) and the corresponding transmit data continuously
until the transmit FIFO is full. It does not determine whether the TxBD to be fetched is already being
processed internally (as a result of a wrap). As the FEC nears the end of the transmission of one frame,
it begins to DMA the data for the next frame. In order to remain one BD ahead of the DMA, it also fetches
the TxBD for the next frame. It is possible that the FEC will fetch from memory a BD that has already been
processed but not yet written back (that is, it is read a second time with the R bit still set). In this case, the
data is fetched and transmitted again.
Using at least three TxBDs fixes this problem for large frames, but not for small frames. To ensure correct
operation for either large or small frames, one of the following must be true:
• The FEC software driver ensures that there is always at least one TxBD with the ready bit cleared.
• Every frame uses more than one TxBD and every TxBD but the last is written back immediately after
the data is fetched.
• The FEC software driver ensures a minimum frame size, n . The minimum number of TxBDs is then
(Tx FIFO Size
÷
(n + 4)) rounded up to the nearest integer (though the result cannot be less than
three). The default Tx FIFO size is 192 bytes; this size is programmable.
Table 17-9/Page
17-17
Correct MIB block counters end addresses to IPSBAR + 0x12FF.
Table 17-11/Page
17-19
Add RMON_R_DROP with an IPSBAR Offset of 0x1280 and a description of ‘Count of frames not
counted correctly’.
Figure 17-26/Page
17-41
Change EMRBR register address from “IPSBAR + 0x11B8” to “IPSBAR + 0x1188”.
Section
20.5.13/Page
20-12
Deleted reference to nonexistent CF bits in the figure and bit descriptions for the GPTFLG2 register.
Figure 23-18/Page
23-18
Remove the two 16-bit divider blocks from timer input, as the divider is not available using external clock
sources.
Section
23.5.1.2.2/Page
23-19
Remove 16-bit divider from equation, as the divider is not available using external clock sources.
Section
25.5.8/Page 25-25
Change end of last sentence from “...and can be written by the host to ‘0’.” to “...and can be written by the
host to ‘1’.”
Table 25-17/Page
25-29
Remove the following information from the BITERR and ACKERR descriptions as these fields are read
only: “To clear this bit, first read it as a one, then write it as a one. Writing zero has no effect.” (This is
a rescindment of a previous documentation errata.)
Change last sentence in ERRINT description from: “To clear this bit, first read it as a one, then write as a
zero. Writing a one has no effect.” to “To clear this bit, first read it as a one, then write a one. Writing a
zero has no effect.”
Add the following information to the BOFFINT and WAKEINT descriptions: “To clear this bit, first read it
as a one, then write it as a one. Writing zero has no effect.”
Table 25-17/Page
25-27
Definition of bits ERRINT and BOFFINT are incorrect for register ESTAT: ERRINT should be bit 1,
BOFFINT should be bit 2. They should be cleared by writing a one instead of a zero.
Table B-7. Rev. 2.3 to Rev. 3 Changes (continued)
Location Description
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3