Motorola ColdFire MCF5281 - Manual (Page 396)

DMA Timers (DTIM0–DTIM3)
21-4 Freescale Semiconductor
Table 21-2. DTMRn Field Descriptions
Field Description
15–8
PS
Prescaler value. Divides the clock input (internal bus clock/(16 or 1) or clock on DTINn)
0x00 1
...
0xFF 256
7–6
CE
Capture edge.
00 Disable capture event output. Timer in reference mode.
01 Capture on rising edge only
10 Capture on falling edge only
11 Capture on any edge
5
OM
Output mode.
0 Active-low pulse for one internal bus clock cycle (12.5-ns resolution at 80 MHz)
1 Toggle output.
4
ORRI
Output reference request, interrupt enable. If ORRI is set when DTERn[REF] is set, a DMA request or an interrupt
occurs, depending on the value of DTXMRn[DMAEN] (DMA request if set, interrupt if cleared).
0 Disable DMA request or interrupt for reference reached (does not affect DMA request or interrupt on capture
function).
1 Enable DMA request or interrupt upon reaching the reference value.
3
FRR
Free run/restart
0 Free run. Timer count continues incrementing after reaching the reference value.
1 Restart. Timer count is reset immediately after reaching the reference value.
2–1
CLK
Input clock source for the timer. Avoid setting CLK when RST is already set. Doing so causes CLK to zero (stop
counting).
00 Stop count
01 Internal bus clock divided by 1
10 Internal bus clock divided by 16. This clock source is not synchronized with the timer; therefore, successive
time-outs may vary slightly.
11 DTINn pin (falling edge)
0
RST
Reset timer. Performs a software timer reset similar to an external reset, although other register values can be written
while RST is cleared. A transition of RST from 1 to 0 resets register values. The timer counter is not clocked unless
the timer is enabled.
0 Reset timer (software reset)
1 Enable timer
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3