Motorola ColdFire MCF5281 - Manual (Page 546)

Queued Analog-to-Digital Converter (QADC)
28-8 Freescale Semiconductor
28.6.2 QADC Test Register (QADCTEST)
The QADCTEST is a reserved register. Attempts to access this register outside of factory test mode will
result in access privilege violation.
28.6.3 Port Data Registers (PORTQA & PORTQB)
QADC ports QA and QB are accessed through the 8-bit PORTQA and PORTQB.
Port QA signals are referred to as PQA[4:3, 1:0] when used as a bidirectional, 4-bit, input/output port. Port
QA can also be used for analog inputs (AN[56:55, 53:52]), external trigger inputs (ETRIG[2:1]), and
external multiplexer address outputs (MA[1:0]).
Port QB signals are referred to as PQB[3:0] when used as a 4-bit, digital input-only port. Port QB can also
be used for non-multiplexed (AN[3:0]) and multiplexed (ANZ, ANY, ANX, ANW) analog inputs.
PORTQA and PORTQB are not initialized by reset.
Table 28-3. QADCMCR Field Descriptions
Bit(s) Name Description
15 QSTOP Stop enable.
1 Force QADC to idle state.
0 QADC operates normally.
14 QDBG Debug enable.
1 Finish any conversion in progress, then freeze in debug mode
0 QADC operates normally.
13–8 — Reserved, should be cleared.
7 SUPV Supervisor/unrestricted data space.
1 All QADC registers are accessible in supervisor mode only; user mode accesses
have no effect and result in a cycle termination error.
0 Only QADCMCR and QADCTEST require supervisor mode access; access to all
other QADC registers is unrestricted
6–0 — Reserved, should be cleared.
7 6 5 4 3 2 1 0
Field — PQA4
(AN56)
(ETRIG2)
PQA3
(AN55)
(ETRIG1)
— PQA1
(AN53)
(MA1)
PQA0
(AN52)
(MA0)
Reset 000 See Note 0 See Note
R/W: R R/W R R/W
Address IPSBAR + 0x19_0006
Figure 28-4. QADC Port QA Data Register (PORTQA)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3