Motorola ColdFire MCF5281 - Manual (Page 195)

Interrupt Controller Modules
Freescale Semiconductor 10-5
The registers and their locations are defined in Table 10-3 . The offsets listed start from the base address
for each interrupt controller. The base addresses for the interrupt controllers are listed below:
Table 10-2. Interrupt Controller Base Addresses
Interrupt Controller Number Base Address
INTC0 IPSBAR + 0xC00
INTC1 IPSBAR + 0xD00
Global IACK Registers Space
1
1
This address space only contains the L1ACK-L7IACK registers. See Section 10.3.7, “Software and Level n
IACK Registers (SWIACKR, L1IACK–L7IACK) " for more information
IPSBAR + 0xF00
Table 10-3. Interrupt Controller Memory Map
Module Offset Bits[31:24] Bits[23:16] Bits[15:8] Bits[7:0]
0x00 Interrupt Pending Register High (IPRH), [63:32]
0x04 Interrupt Pending Register Low (IPRL), [31:1]
0x08 Interrupt Mask Register High (IMRH), [63:32]
0x0c Interrupt Mask Register Low (IMRL), [31:0]
0x10 Interrupt Force Register High (INTFRCH), [63:32]
0x14 Interrupt Force Register Low (INTFRCL), [31:1]
0x18 IRLR[7:1] IACKLPR[7:0] Reserved
0x1C–0x3C Reserved
0x40 Reserved ICR01 ICR02 ICR03
0x44 ICR04 ICR05 ICR06 ICR07
0x48 ICR08 ICR09 ICR10 ICR11
0x4C ICR12 ICR13 ICR14 ICR15
0x50 ICR16 ICR17 ICR18 ICR19
0x54 ICR20 ICR21 ICR22 ICR23
0x58 ICR24 ICR25 ICR26 ICR27
0x5C ICR28 ICR29 ICR30 ICR31
0x60 ICR32 ICR33 ICR34 ICR35
0x64 ICR36 ICR37 ICR38 ICR39
0x68 ICR40 ICR41 ICR42 ICR43
0x6C ICR44 ICR45 ICR46 ICR47
0x70 ICR48 ICR49 ICR50 ICR51
0x74 ICR52 ICR53 ICR54 ICR55
0x78 ICR56 ICR57 ICR58 ICR59
0x7C ICR60 ICR61 ICR62 ICR63
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3