2 initialization sequence, 1 hardware controlled initialization, 2 initialization sequence -30 – Motorola ColdFire MCF5281 User Manual
Page 340: 1 hardware controlled initialization -30
Fast Ethernet Controller (FEC)
17-30
Freescale Semiconductor
NOTE
After the software driver has set up the buffers for a frame, it should set up
the corresponding BDs. The last step in setting up the BDs for a transmit
frame is setting the R bit in the first BD for the frame. The driver must
follow that with a write to TDAR that triggers the FEC to poll the next BD
in the ring.
17.5.2
Initialization Sequence
This section describes which registers are reset due to hardware reset, which are reset by the FEC RISC,
and what locations you must initialize prior to enabling the FEC.
17.5.2.1
Hardware Controlled Initialization
In the FEC, hardware resets registers and control logic that generate interrupts. A hardware reset negates
output signals and resets general configuration bits.
Offset + 0
13
W
Wrap. Written by user.
0 The next buffer descriptor is found in the consecutive location
1 The next buffer descriptor is found at the location defined in ETDSR.
Offset + 0
12
TO2
Transmit software ownership. This field is reserved for use by software. This read/write bit is not
modified by hardware nor does its value affect hardware.
Offset + 0
11
L
Last in frame. Written by user.
0 The buffer is not the last in the transmit frame
1 The buffer is the last in the transmit frame
Offset + 0
10
TC
Transmit CRC. Written by user (only valid if L is set).
0 End transmission immediately after the last data byte
1 Transmit the CRC sequence after the last data byte
Offset + 0
9
ABC
Append bad CRC. Written by user (only valid if L is set).
0 No effect
1 Transmit the CRC sequence inverted after the last data byte (regardless of TC value)
Offset + 0
8–0
Reserved, must be cleared.
Offset + 2
15–0
Data
Length
Data length, written by user.
Data length is the number of octets the FEC should transmit from this BD’s data buffer. It is never
modified by the FEC.
Offset + 4
15–0
A[31:16]
Tx data buffer pointer, bits [31:16]
1
Offset + 6
15–0
A[15:0]
Tx data buffer pointer, bits [15:0]
1
The transmit buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 4. The
buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.
Table 17-30. Transmit Buffer Descriptor Field Definitions (continued)
Word
Field
Description
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3