Motorola ColdFire MCF5281 - Manual (Page 759)

Freescale Semiconductor Index-11
error and status (ESTAT) 25-25
free running timer (TIMER) 25-23
interrupt flag (IFLAG) 25-28
interrupt mask (IMASK) 25-27
module configuration (CANMCR) 25-18
prescaler divide (PRESDIV) 25-22
receive error counter (RXECTR) 25-29
receive mask (RXGMASK, RXnMASK) 25-24
transmit error counter (TXECTR) 25-30
general purpose timers
channel (GPTCn) 20-13
compare force (GPCFORC) 20-6
control 1–2 (GPTCTLn) 20-9
counter (GPTCNT) 20-7
flag 1–2 (GPTFLGn) 20-12
input capture/output compare select (GPTIOS) 20-5
interrupt enable (GPTIE) 20-10
output compare 3 data (GPTOC3D) 20-7
output compare 3 mask (GPTOC3M) 20-6
port data (PORTTn) 20-16
port data direction (GPTDDR) 20-17
pulse accumulator control (GPTPACTL) 20-14
pulse accumulator counter (GPTPACNT) 20-16
pulse accumulator flag (GPTPAFLG) 20-15
system control 1–2 (GPTSCRn) 20-8
, 20-11
toggle-on-overflow (GPTTOV) 20-9
GPIO
port AS pin assignment (PASPAR) 26-21
port B/C/D pin assignment (PBCDPAR) 26-16
port clear output data (CLRn) 26-14
port data direction (DDRn) 26-11
port E pin assignment (PEPAR) 26-17
port EH/EL pin assignment (PEHLPAR) 26-22
port F pin assignment (PFPAR) 26-19
port J pin assignment (PJPAR) 26-20
port output data (PORTn) 26-10
port pin data/set data (PORTnP/SETn) 26-13
port QS pin assignment (PQSPAR) 26-23
port SD pin assignment (PSDPAR) 26-21
port TC pin assignment (PTCPAR) 26-24
port TD pin assignment (PTDPAR) 26-25
port UA pin assignment (PUAPAR) 26-26
I
2
C
address (I2ADR) 24-3
control (I2CR) 24-4
data I/O (I2DR) 24-6
frequency divider (I2FDR) 24-3
status (I2SR) 24-5
interrupt controller
interrupt acknowledge level and priority
(IACKLPRn) 10-11
interrupt control (ICRnx) 10-12
interrupt force high/low (INTFRCHn, INTFRCLn) 10-9
interrupt pending high/low (IPRHn, IPRLn) 10-6
interrupt request level (IRLRn) 10-11
mask high/low (IMRHn, n) 10-7
JTAG
boundary scan 31-5
bypass 31-5
IDCODE 31-4
instruction shift (IR) 31-4
JTAG_CFM_CLKDIV 31-5
TEST_CTRL 31-5
power management
low-power control (LPCR) 7-4
low-power interrupt control (LPICR) 7-2
QADC
control 2–0 (QACRn) 28-10 – 28-14
conversion command word (CCW) 28-24 , 28-53
left-justified signed (LJSRR) 28-27
left-justified unsigned (LJURR) 28-28
module configuration (QADCMCR) 28-7
port data (PORTQA and PORTQB) 28-8
port QA and QB data direction (DDRQA,
DDRQB) 28-9
result word table 28-55
right-justified unsigned result (RJURR) 28-27
status 0–1 (QASRn) 28-17
, 28-23
successive approximation (SAR) 28-34
test (QADCTEST) 28-8
QSPI
address (QAR) 22-7
command RAM (QCRn) 22-8
data (QDR) 22-8
delay (QDLYR) 22-5
interrupt (QIR) 22-6
mode (QMR) 22-3
wrap (QWR) 22-6
reset controller
control (RCR) 29-3
status (RSR) 29-4
SCM
bus master park (MPARK) 8-9
core reset status (CRSR) 8-5
core watchdog control (CWCR) 8-5
core watchdog service (CWSR) 8-7
grouped peripheral access control (GPACRn) 8-15
IPSBAR 8-2
master privilege (MPR) 8-13
peripheral access control (PACRn) 8-13
RAMBAR 5-1
, 8-3
SDRAM controller
address and control 1–0 (DACRn) 15-6
control (DCR) 15-4
mask (DMRn) 15-8
mode register
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3