Motorola ColdFire MCF5281 - Manual (Page 81)

Enhanced Multiply-Accumulate Unit (EMAC)
Freescale Semiconductor 3-3
3.2 Memory Map/Register Definition
The following table and sections explain the MAC registers:
3.2.1 MAC Status Register (MACSR)
The MAC status register (MACSR) contains a 4-bit operational mode field and condition flags.
Operational mode bits control whether operands are signed or unsigned and whether they are treated as
integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding
is performed. Negative, zero, and multiple overflow condition flags are also provided.
Table 3-1. EMAC Memory Map
BDM
1
Register
Width
(bits)
Access Reset Value Section/Page
0x804 MAC Status Register (MACSR) 32 R/W 0x0000_0000 3.2.1/3-3
0x805 MAC Address Mask Register (MASK) 32 R/W 0xFFFF_FFFF 3.2.2/3-5
0x806 MAC Accumulator 0 (ACC0) 32 R/W Undefined 3.2.3/3-6
0x807 MAC Accumulator 0,1 Extension Bytes (ACCext01) 32 R/W Undefined 3.2.4/3-7
0x808 MAC Accumulator 2,3 Extension Bytes (ACCext23) 32 R/W Undefined 3.2.4/3-7
0x809 MAC Accumulator 1 (ACC1) 32 R/W Undefined 3.2.3/3-6
0x80A MAC Accumulator 2 (ACC2) 32 R/W Undefined 3.2.3/3-6
0x80B MAC Accumulator 3 (ACC3) 32 R/W Undefined 3.2.3/3-6
1 The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more
information see
Chapter 43, “Debug Module.”
BDM: 0x804 (MACSR) Access: Supervisor read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PAVn OMC S/U F/I R/T N Z V EV
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 3-2. MAC Status Register (MACSR)
Table 3-2. MACSR Field Descriptions
Field Description
31–12 Reserved, must be cleared.
11–8
PAVn
Product/accumulation overflow flags. Contains four flags, one per accumulator, that indicate if past MAC or
MSAC instructions generated an overflow during product calculation or the 48-bit accumulation. When a
MAC or MSAC instruction is executed, the PAVn flag associated with the destination accumulator forms the
general overflow flag, MACSR[V]. Once set, each flag remains set until V is cleared by a
move.l, MACSR
instruction or the accumulator is loaded directly.
Bit 11: Accumulator 3
...
Bit 8: Accumulator 0
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3