Motorola ColdFire MCF5281 - Manual (Page 479)

FlexCAN
Freescale Semiconductor 25-9
• Writing the Data bytes
• Writing the Control/Status word (active Code, Length)
NOTE
The first and last steps are mandatory!
Starting from the last step, this MB will participate in the internal arbitration process, which takes place
every time the CAN bus is sensed as free by the receiver or at the inter-frame space, and there is at least
one MB ready for transmission. This internal arbitration process is intended to select the MB from which
the next frame is transmitted.
When this process is over, and there is a ‘winner’ MB for transmission, the frame is transferred to the serial
message buffer (SMB) for transmission (Move Out).
While transmitting, the FlexCAN transmits up to eight data bytes, even if the DLC is bigger in value.
At the end of the successful transmission, the value of the free-running timer (which was captured at the
beginning of the Identifier field on the CAN bus), is written into the “Time Stamp” field in the MB, the
Code field in the Control/Status word of the MB is updated and a status flag is set in the IFLAG register.
25.4.2 Receive Process
The CPU prepares or changes an MB for frame reception by executing the following steps:
• Writing the control/status word to hold Rx MB inactive (code = 0000).
• Writing the ID_HIGH and ID_LOW words.
• Writing the control/status word to mark the Rx MB as active and empty.
NOTE
The first and last steps are mandatory!
Starting from the last step, this MB is an active receive buffer and will participate in the internal matching
process, which takes place every time the receiver receives an error-free frame. In this process, all active
receive buffers compare their ID value to the newly received one, and if a match occurs, the frame is
transferred (Move In) to the first (that is, lowest entry) matching MB. The value of the free-running timer
(which was captured at the beginning of the Identifier field on the CAN bus) is written into the “Time
Stamp” field in the MB, the ID field, data field (8 bytes at most) and the LENGTH field are stored, the
Code field is updated and a status flag is set in the IFLAG register.
The CPU should read a receive frame from its MB in the following way:
• Control/status word (mandatory—activates internal lock for this buffer).
• ID (Optional—needed only if a mask was used).
• Data field word(s).
• Free-running timer (Releases internal lock —optional).
The read of the free-running timer is not mandatory. If not executed, the MB remains locked, unless the
CPU starts the read process for another MB. Note that only a single MB is locked at a time. The only
mandatory CPU read operation is of the Control/Status word, to assure data coherency. If the BUSY bit is
set in the MB code, then the CPU should defer until this bit is negated.
The CPU should synchronize to frame reception by the status flag for the specific MB (see
Section 25.5.10, “Interrupt Flag Register (IFLAG) ”), and not by the control/status word code field for that
MB. This is because polling the control/status word may lock the MB (see above), and the Code may
change before the full frame is received into the MB.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3