3 low-power mode operation, 4 block diagram, Low-power mode operation -2 – Motorola ColdFire MCF5281 User Manual

Page 172: Block diagram -2

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Clock Module

9-2

Freescale Semiconductor

9.3

Low-power Mode Operation

This subsection describes the operation of the clock module in low-power and halted modes of operation.
Low-power modes are described in

Chapter 7, “Power Management

.”

Table 9-1

shows the clock module

operation in low-power modes.

Table 9-1. Clock Module Operation in Low-power Modes

During wakeup from a low-power mode, the Flash clock always clocks through at least 16 cycles before
the CPU clocks are enabled. This allows the Flash module time to recover from the low-power mode, and
software can immediately resume fetching instructions from memory.

In wait and doze modes, the system clocks to the peripherals are enabled, and the clocks to the CPU, Flash,
and SRAM are stopped. Each module can disable its clock locally at the module level.

In stop mode, all system clocks are disabled. There are several options for enabling or disabling the PLL
or crystal oscillator in stop mode, compromising between stop mode current and wakeup recovery time.
The PLL can be disabled in stop mode, but requires a wakeup period before it can relock. The oscillator
can also be disabled during stop mode, but requires a wakeup period to restart.

When the PLL is enabled in stop mode (STPMD[1:0]), the external CLKOUT signal can support systems
using CLKOUT as the clock source.

There is also a fast wakeup option for quickly enabling the system clocks during stop recovery. This
eliminates the wakeup recovery time but at the risk of sending a potentially unstable clock to the system.
To prevent a non-locked PLL frequency overshoot when using the fast wakeup option, change the RFD
divisor to the current RFD value plus one before entering stop mode.

In external clock mode, there are no wakeup periods for oscillator startup or PLL lock.

9.4

Block Diagram

Figure

shows a block diagram of the entire clock module. The PLL block in this diagram is expanded in

detail in

Figure 9-2

.

Low-power Mode

Clock Operation

Mode Exit

Wait

Clocks sent to peripheral modules only

Exit not caused by clock module, but normal

clocking resumes upon mode exit

Doze

Clocks sent to peripheral modules only

Exit not caused by clock module, but normal

clocking resumes upon mode exit

Stop

All system clocks disabled

Exit not caused by clock module, but clock

sources are re-enabled and normal clocking

resumes upon mode exit

Halted

Normal

Exit not caused by clock module

MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

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