Motorola ColdFire MCF5281 - Manual (Page 322)

Fast Ethernet Controller (FEC)
17-12 Freescale Semiconductor
17.4.5 Transmit Descriptor Active Register (TDAR)
The TDAR is a command register which the user writes to indicate the transmit descriptor ring is updated
(transmit buffers have been produced by the driver with the ready bit set in the buffer descriptor).
When the register is written, the TDAR bit is set. This value is independent of the data actually written by
the user. When set, the FEC polls the transmit descriptor ring and processes transmit frames (provided
ECR[ETHER_EN] is also set). After the FEC polls a transmit descriptor that is a ready bit not set, FEC
clears the TDAR bit and ceases transmit descriptor ring polling until the user sets the bit again, signifying
additional descriptors are placed into the transmit descriptor ring.
The TDAR register is cleared at reset, when ECR[ETHER_EN] is cleared, or when ECR[RESET] is set.
17.4.6 Ethernet Control Register (ECR)
ECR is a read/write user register, though hardware may alter fields in this register as well. The ECR
enables/disables the FEC.
Table 17-7. RDAR Field Descriptions
Field Description
31–25 Reserved, must be cleared.
24
RDAR
Set to 1 when this register is written, regardless of the value written. Cleared by the FEC device when no additional
empty descriptors remain in the receive ring. Also cleared when ECR[ETHER_EN] is cleared.
23–0 Reserved, must be cleared.
IPSBAR
Offset:
0x1014 Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
TDAR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17-5. Transmit Descriptor Active Register (TDAR)
Table 17-8. TDAR Field Descriptions
Field Description
31–25 Reserved, must be cleared.
24
TDAR
Set to 1 when this register is written, regardless of the value written. Cleared by the FEC device when no additional
ready descriptors remain in the transmit ring. Also cleared when ECR[ETHER_EN] is cleared.
23–0 Reserved, must be cleared.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3