Document Outline

• 1. Introduction
  • 1.1 Pin configuration
  • 1.2 Pin description
  • 1.3 Functional diagram
  • 1.4 Block diagram
  • 1.5 Special function registers
  • 1.6 Memory organization
• 2. Clocks
  • 2.1 Enhanced CPU
  • 2.2 Clock definitions
    • 2.2.1 Oscillator Clock (OSCCLK)
  • 2.3 External crystal oscillator option
    • 2.3.1 Low speed oscillator option
    • 2.3.2 Medium speed oscillator option
    • 2.3.3 High speed oscillator option
  • 2.4 Clock output
  • 2.5 On-chip RC oscillator option
  • 2.6 Watchdog oscillator option
  • 2.7 External clock input option
  • 2.8 Clock sources switch on the fly
  • 2.9 Oscillator Clock (OSCCLK) wake-up delay
  • 2.10 CPU Clock (CCLK) modification: DIVM register
  • 2.11 Low power select
• 3. Interrupts
  • 3.1 Interrupt priority structure
  • 3.2 External Interrupt pin glitch suppression
• 4. I/O ports
  • 4.1 Port configurations
  • 4.2 Quasi-bidirectional output configuration
  • 4.3 Open drain output configuration
  • 4.4 Input-only configuration
  • 4.5 Push-pull output configuration
  • 4.6 Port 0 and Analog Comparator functions
  • 4.7 Additional port features
• 5. Power monitoring functions
  • 5.1 Brownout detection
  • 5.2 Power-on detection
  • 5.3 Power reduction modes
• 6. Reset
  • 6.1 Reset vector
• 7. Timers 0 and 1
  • 7.1 Mode 0
  • 7.2 Mode 1
  • 7.3 Mode 2
  • 7.4 Mode 3
  • 7.5 Mode 6
  • 7.6 Timer overflow toggle output
• 8. Real-time clock system timer
  • 8.1 Real-time clock source
  • 8.2 Changing RTCS1/RTCS0
  • 8.3 Real-time clock interrupt/wake-up
    • 8.3.1 Real-time clock read back
  • 8.4 Reset sources affecting the Real-time clock
• 9. Capture/Compare Unit (CCU)
  • 9.1 CCU Clock (CCUCLK)
  • 9.2 CCU Clock prescaling
  • 9.3 Basic timer operation
  • 9.4 Output compare
  • 9.5 Input capture
  • 9.6 PWM operation
  • 9.7 Alternating output mode
  • 9.8 Synchronized PWM register update
  • 9.9 HALT
  • 9.10 PLL operation
  • 9.11 CCU interrupt structure
• 10. UART
  • 10.1 Mode 0
  • 10.2 Mode 1
  • 10.3 Mode 2
  • 10.4 Mode 3
  • 10.5 SFR space
  • 10.6 Baud Rate generator and selection
  • 10.7 Updating the BRGR1 and BRGR0 SFRs
  • 10.8 Framing error
  • 10.9 Break detect
  • 10.10 More about UART Mode 0
  • 10.11 More about UART Mode 1
  • 10.12 More about UART Modes 2 and 3
  • 10.13 Framing error and RI in Modes 2 and 3 with SM2 = 1
  • 10.14 Break detect
  • 10.15 Double buffering
  • 10.16 Double buffering in different modes
  • 10.17 Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)
  • 10.18 The 9th bit (bit 8) in double buffering (Modes 1, 2, and 3)
  • 10.19 Multiprocessor communications
  • 10.20 Automatic address recognition
• 11. I2C interface
  • 11.1 I2C data register
  • 11.2 I2C slave address register
  • 11.3 I2C control register
  • 11.4 I2C Status register
  • 11.5 I2C SCL duty cycle registers I2SCLH and I2SCLL
  • 11.6 I2C operation modes
    • 11.6.1 Master Transmitter mode
    • 11.6.2 Master Receiver mode
    • 11.6.3 Slave Receiver mode
    • 11.6.4 Slave Transmitter mode
• 12. Serial Peripheral Interface (SPI)
  • 12.1 Configuring the SPI
  • 12.2 Additional considerations for a slave
  • 12.3 Additional considerations for a master
  • 12.4 Mode change on SS
  • 12.5 Write collision
  • 12.6 Data mode
  • 12.7 SPI clock prescaler select
• 13. Analog comparators
  • 13.1 Comparator configuration
  • 13.2 Internal reference voltage
  • 13.3 Comparator input pins
  • 13.4 Comparator interrupt
  • 13.5 Comparators and power reduction modes
  • 13.6 Comparators configuration example
  • 13.7 Programmable Gain Amplifier (PGA)
• 14. Keypad interrupt (KBI)
• 15. Watchdog timer (WDT)
  • 15.1 Watchdog function
  • 15.2 Feed sequence
  • 15.3 Watchdog clock source
  • 15.4 Watchdog Timer in Timer mode
  • 15.5 Power-down operation
  • 15.6 Periodic wake-up from power-down without an external oscillator
• 16. Additional features
  • 16.1 Software reset
  • 16.2 Dual Data Pointers
• 17. Data EEPROM
  • 17.1 Data EEPROM read
  • 17.2 Data EEPROM write
  • 17.3 Hardware reset
  • 17.4 Multiple writes to the DEEDAT register
  • 17.5 Sequences of writes to DEECON and DEEDAT registers
  • 17.6 Data EEPROM Row Fill
  • 17.7 Data EEPROM Block Fill
• 18. Flash memory
  • 18.1 General description
  • 18.2 Features
  • 18.3 Flash programming and erase
  • 18.4 Using Flash as data storage: IAP-Lite
  • 18.5 In-circuit programming (ICP)
  • 18.6 ISP and IAP capabilities of the P89LPC9321
  • 18.7 Boot ROM
  • 18.8 Power on reset code execution
  • 18.9 Hardware activation of Boot Loader
  • 18.10 In-system programming (ISP)
  • 18.11 Using the In-system programming (ISP)
  • 18.12 In-application programming (IAP)
  • 18.13 IAP authorization key
  • 18.14 Flash write enable
  • 18.15 Configuration byte protection
  • 18.16 IAP error status
  • 18.17 User configuration bytes
  • 18.18 User security bytes
  • 18.19 Boot Vector register
  • 18.20 Boot status register
• 19. Instruction set
• 20. Legal information
  • 20.1 Definitions
  • 20.2 Disclaimers
  • 20.3 Trademarks
• 21. Tables
• 22. Figures
• 23. Contents