4 dac input data register (daci) -12, 5 dac output data register (daco) -12, 4 dac input data register (daci) – Maxim Integrated MAXQ7666 User Manual
Page 102: 5 dac output data register (daco)
3.2.4 DAC Input Data Register (DACI)
Register Description:
DAC Input Data Register
Register Name:
DACI
Register Address:
Module 05h, Index 04h
Bits 15 to 12: Reserved. Read returns 0, write ignored.
Bits 11 to 0: DAC Input Data 11 to 0 (DACI.11 to DACI.0). This register holds input data for DAC conversion.
3.2.5 DAC Output Data Register (DACO)
Register Description:
DAC Output Data Register
Register Name:
DACO
Register Address:
Module 05h, Index 06h
Bits 15 to 12: Reserved. Read returns 0, write ignored.
Bits 11 to 0: DAC Output Data 11 to 0 (DACO.11 to DACO.0). This register holds output data for DAC conversion. Data from the DAC
input register is transferred to this output register for DAC conversion as controlled by the DACLD2:DACLD0 bits.
MAXQ7665/MAXQ7666 User’s Guide
3-12
Bit #
15
14
13
12
11
10
9
8
Name —
—
—
—
DACI.11
DACI.10
DACI.9
DACI.8
Reset
0 0 0 0 0 0 0 0
Access
r r r r rw
rw
rw
rw
Bit #
7
6
5
4
3
2
1
0
Name DACI.7
DACI.6
DACI.5
DACI.4
DACI.3
DACI.2
DACI.1
DACI.0
Reset
0 0 0 0 0 0 0 0
Access
rw rw rw rw rw rw rw rw
r = read, w = write
Note: This register is cleared to 0000h on all forms of reset.
Bit #
15
14
13
12
11
10
9
8
Name —
—
—
—
DACO.11
DACO.10
DACO.9
DACO.8
Reset
0 0 0 0 0 0 0 0
Access
r r r r rw rw rw rw
Bit #
7
6
5
4
3
2
1
0
Name DACO.7
DACO.6
DACO.5
DACO.4
DACO.3
DACO.2
DACO.1
DACO.0
Reset
0 0 0 0 0 0 0 0
Access
rw rw rw rw rw rw rw rw
r = read, w = write
Note: This register is cleared to 0000h on all forms of reset.
Maxim Integrated