Maxim Integrated MAXQ7666 - Manual (Page 163)

MAXQ7665/MAXQ7666 User’s Guide
4-33
Bit 6: Increment/Decrement Select (INCDEC). This bit determines the C0DP’s auto-increment/decrement function when AID bit is set
to logic 1. When INCDEC is set to logic 0, the contents of C0DP are decremented by 1 after a read/write access to the C0DB register.
When INCDEC is 1, the contents of the C0DP are incremented by 1 after a read/write access to the C0DB register.
Bit 5: Automatic Increment/Decrement Enable (AID). This bit enables automatic increment or decrement of the CAN data pointer
(C0DP) after the CAN data buffer (C0DB) has been accessed. The actual increment/decrement function is dependent on the setting
of the INCDEC bit. When AID is set to logic 1, the contents of the C0DP are incremented (or decremented) by 1 after a read/write
access to the C0DB register. When AID is cleared to 0, a read/write access to the C0DB register has no effect on the contents of the
C0BP register.
Bits 4 and 3: CAN 0 Baud-Rate Prescale Bits 7 and 6 (C0BPR7 and C0BPR6). The C0BPR7 and C0BPR6 bits establish the two
high-order bits associated with the 8-bit baud-rate prescaler in the CAN 0 controller. Note that the C0BPR7 and C0BPR6 bits cannot
be written when the SWINT bit in the CAN 0 control register is cleared to 0. The remaining CAN baud-rate prescale bits are in the CAN
0 bus timing register (C0BT0).
Bit 1: CAN 0 Bus Activity Interrupt Enable (C0BIE). When this bit is set to logic 1, detecting a CAN bus activity initiates an interrupt.
When this bit is set to logic 0, the interrupt capability caused by CAN bus activity is disabled.
Bit 0: CAN 0 Interrupt Enable (C0IE). When this bit is set to logic 1, a change of CAN status register initiates an interrupt if the cor-
responding ERIE or STIE bit in the CAN control register is also set. When this bit is set to logic 0, the interrupt capability caused by
change of CAN status register is disabled.
4.2.4.7 CAN 0 Data Pointer Register (C0DP)
Register Description: CAN 0 Data Pointer Register
Register Name: C0DP
Register Address: Module 04h, Index 06h
Bits 15 to 0: CAN 0 Data Pointer Register Bits 15 to 0 (C0DP.15 to C0DP.0). This register is used as a pointer for direct memory
access to the dual port memory. Only the lower seven bits are significant; the other high-order bits are tied to 0. To access the dual port
memory, a valid address in the range of 00h to 7Fh must be presented in this register. The contents of this register can be automatical-
ly incremented or decremented after a read/write access to the C0DB register by setting the AID and INCDEC bit in the COR register.
Note that the dual port memory is synchronous memory and its read pointer must be activated before a memory read. A write to C0DP
or a read from C0DB automatically activates the C0DP as a read pointer and remains in effect until the C0DP is used as a write point-
er. In this case, C0DP must be reactivated by a write of C0DP before reading data from C0DB, or it must be reactivated by a back-to-
back read from C0DB if the auto-increment/decrement function is disabled. Valid data is presented by the second read operation. If it
is suspected that the data at the memory location addressing by the C0DP has been changed, the C0DP must be reactivated to ensure
the new data has been pushed to the C0DB register.
Bit # 15 14 13 12 11 10 9 8
Name C0DP.15 C0DP.14 C0DP.35 C0DP.12 C0DP.11 C0DP.10 C0DP.9 C0DP.8
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
Bit # 7 6 5 4 3 2 1 0
Name C0DP.7 C0DP.6 C0DP.5 C0DP.4 C0DP.3 C0DP.2 C0DP.1 C0DP.0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
r = read, w = write
Note: This register is cleared to 0000h on all forms of reset.
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