Maxim Integrated MAXQ7666 - Manual (Page 181)

MAXQ7665/MAXQ7666 User’s Guide
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4.3.1.3 Error Frame
The error frame is transmitted by a CAN controller when the CAN processor detects a bus error. The error frame is composed of two
different fields: the superposition of the error flags from different nodes and the error delimiter.
The error frame is composed of six dominant bits that violate the CAN specification bit stuffing rule. If either of the CAN processors
detects an error condition, that CAN processor transmits an error frame. When this happens, all nodes on the bus detect the bit stuff
error condition and transmit their own error frame. The superpositioning of all these error frames leads to a total error frame length
between 6 and 12 bits, depending on the response time and number of nodes in the system. Any messages (data or remote frame)
received by the CAN processors (successful or not) that are followed by an error frame are discarded. After the transmission of an error
flag, each CAN processor sends an error delimiter (eight recessive bits) and monitors the bus until it detects the change from the dom-
inant to recessive bit level. The CAN modules issue an error frame each time an error frame is detected. Following a series of error
frames, the CAN modules enter into an error passive mode. In the error passive mode, the CAN processors transmit six recessive bits
and wait until six equal bits of the same polarity have been detected. At this point, the CAN processor begins the next internal receive
or transmission operation.
4.3.1.4 Overload Frame
The overload frame provides an extra delay between data or remote frames. The overload frame is composed of two different fields:
the overload flag and the overload delimiter.
There are three conditions that lead to the transmission of an overload flag:
1) The internal conditions of a CAN receiver require a delay before the next data or remote frame is sent. The MAXQ7665/
MAXQ7666 CAN controller is designed to prevent this condition for data rates at or below the 1Mbps data rate.
2) The CAN processor detects a dominant bit at the first and second bit position of the intermission.
3) If the CAN processor detects a dominant bit at the 8th bit of an error delimiter or overload delimiter, it starts transmitting an
overload frame.
The error counters are not incremented as a result of number 3. The CAN processor only starts an overload frame at the first bit of an
expected Intermission if initiated by condition 1. Conditions 2 and 3 result in the CAN processor transmitting an overload frame, starting
one bit after detecting the dominant bit. The overload flag consists of six dominant bits that correspond to an error flag. Because the
overload frame is only transmitted at the first bit time of the interframe space, it is possible for the CAN processor to discriminate between
an error frame and an overload frame. The overload flag destroys the intermission field. When such a condition is detected, the CAN
processor detects the overload condition and begins transmitting an overload frame. After the transmission of an overload frame, the
CAN processors monitor the bus for a dominant to recessive level change. The CAN processor then begins the transmission of six addi-
tional recessive bits, for a total of seven recessive bits on the bus. The overload delimiter consists of eight recessive bits.
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