Maxim Integrated MAXQ7666 - Manual (Page 82)

MAXQ7665/MAXQ7666 User’s Guide
2-10
2.2.4 Analog Status Register (ASR)
The ASR register reports the status of the DVDD and DVDDIO supply brownout detection.
Register Description: Analog Status Register
Register Name: ASR
Register Address: Module 05h, Index 0Bh
Bit 15: I/O Voltage Brownout Comparator Level (VIOLVL). This bit reflects the DVDDIO voltage brownout comparator’s current out-
put state when read. This bit is set to logic 1 when the DVDDIO supply is higher than the threshold level (as programmed by the
VIOBI[1:0] threshold bits in the VMC register) and is cleared to logic 0 when the supply voltage is below the threshold level. At power-
up or when the DVDDIO voltage monitor is disabled (VIBE = 0), this bit is cleared to 0.
Bit 14: Digital Voltage Brownout Comparator Level (DVLVL). This bit reflects the DVDD voltage brownout comparator’s current out-
put state when read. This bit is set to logic 1 when the DVDD supply is higher than the threshold level (as programmed by the VDBI[1:0]
threshold bits in the VMC register) and is cleared to logic 0 when the supply voltage is below the threshold level. At power-up or when
the DVDD voltage monitor is disabled (VDBE = 0), this bit is cleared to 0.
Bits 13, 12, 10 to 7, 3, and 0: Reserved. Read 0, write ignored.
Bit 11: High-Frequency Oscillator Ready (XHFRY). See Section 5 for more information on this register bit.
Bit 6: External High-Frequency Oscillator Failure Flag (HFFINT). See Section 5 for more information on this register bit.
Bit 5: I/O Voltage Brownout Flag (VIOBI). This flag is set to logic 1 when a brownout interrupt condition is detected on the DVDDIO
supply voltage. This bit is cleared after reading from the ASR register. If enabled (VIOBIE = 1), the DVDDIO brownout interrupt is gen-
erated by this register bit.
Bit 4: Digital Brownout Flag (DVBI). This flag is set to logic 1 when a brownout interrupt condition is detected on the DVDD supply
voltage. This bit is cleared after reading from the ASR register. If enabled (DVBIE = 1), the DVDD brownout interrupt is generated by
this register bit.
Bit 2: ADC Overrun Flag (ADCOV). See Section 3 for more information on this register bit.
Bit 1: ADC Data Ready Flag (ADCRY). See Section 3 for more information on this register bit.
Bit # 15 14 13 12 11 10 9 8
Name VIOLVL DVLVL — — XHFRY — — —
Reset 0 0 0 0 0 0 0 0
Access r r r r r r r r
Bit # 7 6 5 4 3 2 1 0
Name — HFFINT VIOBI DVBI — ADCOV ADCRY —
Reset 0 0 0 0 0 0 0 0
Access r r r r r r r r
r = read
Note: The ADCOV bit is cleared by all forms of reset. All other bits are reset only by POR. Reading the ASR resets to 0 all the status flag bits except
VIOLVL and DVLVL.
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