Maxim Integrated MAXQ7666 - Manual (Page 122)

MAXQ7665/MAXQ7666 User’s Guide
3-32
In dual-edged conversions, it is up to the user to provide the required power-up and acquisition delay as explained in Table 3-9.
a) If ADC is in auto shutdown state, a minimum of 13 ADC clock cycles power-up and acquisition delay is required, in addition
to 80 cycles PGA settling delay (PGA gain > 1) and 13 cycles ADC conversion delay for a total of at least 107 ADC clock cycles
before the 12-bit result is available.
b) If ADC is not in auto shutdown state, a minimum of 3 ADC clock cycles acquisition delay is required, in addition to 40 cycles
PGA settling delay (PGA gain > 1) and 13 cycles ADC conversion delay for a total of at least 57 ADC clock cycles before the
12-bit result is available.
Figure 3-12 shows dual-edge-controlled ADC conversion when the ADC is in auto shutdown state and the PGA is > 1.
In dual-edge conversion, the power-up and acquisition is triggered by the rising edge of the ADC conversion start source signal
ADC_CNVST. At the falling edge, the ADC starts conversion and a 12-bit result is written to the ADC result register in 13 ADC clock
cycles. The advantage of dual-edge mode is, depending on the analog input signal’s source impedance, the user can provide addi-
tional acquisition time if required. Also, in dual-edge mode the user can determine the exact sample instant. This can be very useful
in applications where a signal must be sampled precisely every so many microseconds, for example.
3.3.11 ADC Interrupts
The MAXQ7665/MAXQ7666 ADC can generate an interrupt under the following conditions:
• ADC Data Ready
• ADC Overrun
The ADC data ready interrupt is generated when the conversion on a channel is complete and a 12-bit result is written into the ADC
data register. The ADC data ready (ADCRY) flag in the analog status register (ASR) is also set when a conversion is complete. The
ADCIE bit in the analog interrupt register (AIE) must be set for the interrupt to be generated. Otherwise, only the ADCRY status flag is
set and the interrupt is not generated. The ADCRY flag is cleared when the ADC data register (ADCD) is read.
The ADC overrun interrupt is generated when an ADC result overrun occurs. The ADC result overrun occurs if the ADC data register
is overwritten with a new result before the previous result is read. The ADC overrun (ADCOV) flag in the ASR is set when an overrun
occurs. An interrupt is generated only if the AORIE bit in the AIE register is set, otherwise, only the status flag is set. The ADCOV flag
is cleared when the analog status register (ASR) is read.
The ADC data ready and ADC overrun interrupts are globally enabled/disabled by the IM5 bit (in the IMR register) and the IGE bit (in
the IC register).
Figure 3-12. Dual-Edge ADC Conversion Timing; ADC Previously Off and PGA > 1
ADCBY
ADCDATA
ADCCLK
ADC_CNVST
DATA (n-1) DATA (n)
1 13
CONVERSION (n)
POWER-UP AND ACQUISITION
(UNDER USER CONTROL;
MINIMUM: 93 CYCLES IF ADCASD = 1; 43 CYCLES IF ADCASD = 0)
Maxim Integrated