Maxim Integrated MAXQ7666 - Manual (Page 277)

MAXQ7665/MAXQ7666 User’s Guide
9-4
9.1.1 SPI Pins
The SPI signals are shown in Table 9-1.
Table 9-1. MAXQ7665/MAXQ7666 SPI Pins
9.2 SPI Peripheral Registers
The MAXQ7665/MAXQ7666 SPI peripheral registers are described here. All the SPI peripheral registers are directly accessible by the
microcontroller through the module/index address.
9.2.1 SPI Data Buffer Register (SPIB)
Register Description: SPI Data Buffer Register
Register Name: SPIB
Register Address: Module 01h, Index 06h
Bits 15 to 0: SPIB Data Bits 15 to 0 (SPIB.15 to SPIB.0). Data for SPI is read from or written to this location. The serial transmit and
receive buffers are separate but both are addressed at this location. Write access is allowed only outside of the transfer cycle. When
the STBY bit (SPICN.7) is set, write attempts are blocked and cause a write collision error.
PIN NUMBER
SPI EXTERNAL
SIGNAL
48 56
MASTER MODE USE SLAVE MODE USE
MISO—Master In,
Slave Out
35 Input to serial shift register.
Output from serial shift register when selected. Data sent
most significant bit first.
MOSI—Master Out,
Slave In
34
Output from serial shift register. Data
sent most significant bit first.
Input to serial shift register when selected.
SCLK 33
Serial shift clock sourced to slave
device(s).
Serial shift clock from an external master.
SS 32
(Optional) Mode-fault-detection input
if enabled (MODFE = 1).
Slave select input.
—
Bit # 15 14 13 12 11 10 9 8
Name SPIB.15 SPIB.14 SPIB.13 SPIB.12 SPIB.11 SPIB.10 SPIB.9 SPIB.8
Reset 0 0 0 0 0 0 0 0
Access rw* rw* rw* rw* rw* rw* rw* rw*
Bit # 7 6 5 4 3 2 1 0
Name SPIB.7 SPIB.6 SPIB.5 SPIB.4 SPIB.3 SPIB.2 SPIB.1 SPIB.0
Reset 0 0 0 0 0 0 0 0
Access rw* rw* rw* rw* rw* rw* rw* rw*
r = read, w = write, * = write allowed only when STBY = 0
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