2 spi control register (spicn) -5 – Maxim Integrated MAXQ7666 User Manual
Page 278
9.2.2 SPI Control Register (SPICN)
Register Description:
SPI Control Register
Register Name:
SPICN
Register Address:
Module 01h, Index 07h
Bits 15 to 8: Reserved. Read 0, write ignored.
Bit 7: SPI Transfer Busy Flag (STBY). This bit is used to indicate the current transmit/receive activity of the SPI module. STBY is set
to 1 when an SPI transfer cycle starts and is cleared to 0 when the transfer cycle is completed. This bit is controlled by hardware and
is read only for user software.
0 = SPI module is idle—no transfer in progress.
1 = SPI transfer in progress.
Bit 6: SPI Transfer Complete Flag (SPIC). This bit signals the completion of an SPI transfer cycle. This bit must be cleared to 0 by
software once set. Setting this bit to logic 1 causes an interrupt if enabled.
0 = No SPI transfers have completed since the bit was last cleared.
1 = SPI transfer complete.
Bit 5: Receive Overrun Flag (ROVR). This bit indicates a receive overrun has occurred. A receive overrun results when a received
character is ready to be transferred to the SPI receive data buffer before the previous character in the data buffer is read. The most
recent receive data is lost. This bit must be cleared to 0 by software once set. Setting this bit to logic 1 causes an interrupt if enabled.
0 = No receive overrun has occurred.
1 = Receive overrun occurred.
Bit 4: Write Collision Flag (WCOL). This bit signifies that an attempt was made by software to write the SPI buffer (SPIB) while a trans-
fer was in progress (STBY = 1). Such attempts will always be blocked. This bit must be cleared to 0 by software once set. Setting this
bit to logic 1 causes an interrupt if enabled.
0 = No write collision has been detected.
1 = Write collision detected.
MAXQ7665/MAXQ7666 User’s Guide
9-5
Bit #
15
14
13
12
11
10
9
8
Name — — — — — — — —
Reset 0 0 0 0 0 0 0 0
Access r r r r r r r r
Bit #
7
6
5
4
3
2
1
0
Name
STBY SPIC ROVR WCOL MODF MODFE MSTM SPIEN
Reset 0 0 0 0 0 0 0 0
Access r rw rw rw rw rw rw rw
r = read, w = write
Maxim Integrated