Maxim Integrated MAXQ7666 User Manual
Page 142
MAXQ7665/MAXQ7666 User’s Guide
4-12
CAN 0 Bus Timing Register 1 (C0BT1)
Bit 7: CAN Sampling Rate (SMP). The SMP bit determines the number of samples to be taken during each receive bit time.
Programming SMP = 0 takes only one sample during each bit time. Programming SMP = 1 directs the CAN logic to take three sam-
ples during each bit time, and to use a majority voting circuit to determine the final bit value. When SMP is set to 1, two additional t
QU
clock cycles are be added to time segment 1. SMP should not be set to 1 when the baud-rate prescale value (BRPV) is less than 4.
This bit can only be modified during a software initialization (SWINT = 1).
Bits 6, 5, 4: CAN Time Segment 2 Select (TSEG26, TSEG25, TSEG24). The eight states defined by the TSEG26, TSEG25, and
TSEG24 bits determine the number of clock cycles in the phase segment 2 portion of the nominal bit time, which occurs after the sam-
ple time. These bits can only be modified during a software initialization (SWINT = 1).
Bits 3 to 0: CAN Time Segment 1 Select (TSEG13 to TSEG10). The 16 states defined by the TSEG13–TSEG10 bits determine the
number of clock cycles in the phase segment 1 portion of the nominal bit time, which occurs before the sample time. These bits can
only be modified during a software initialization (SWINT = 1).
r = read, w = write (allowed only when SWINT = 1 via C0DP/C0DB)
Bit #
7 6 5 4 3 2 1 0
Name
SMP TSEG26 TSEG25 TSEG24 TSEG13 TSEG12 TSEG11 TSEG10
Reset
0 0 0 0 0 0 0 0
Access
rw rw rw rw rw rw rw rw
Dual Port
Address
02h(H)
TSEG26
TSEG25
TSEG24
TIME SEGMENT 2 LENGTH
0
0
0
Invalid
0
0
1
2 t
QU
(2)
0
1
0
3 t
QU
(3)
. . .
. . .
. . .
. . .
1
1
0
7 t
QU
(7)
1
1
1
8 t
QU
(8)
Note: Number in parentheses is the TS2_LEN value used in bit timing calculations.
TSEG13
TSEG12
TSEG11
TSEG10
TIME SEGMENT 2 LENGTH
0
0
0
0
Invalid
0
0
0
1
2 t
QU
(2)
0
1
1
0
3 t
QU
(3)
. . .
. . .
. . .
. . .
. . .
1
1
1
0
15 t
QU
(15)
1
1
1
1
16 t
QU
(16)
Note: Number in parentheses is the TS1_LEN value used in bit timing calculations.
Maxim Integrated