Maxim Integrated MAXQ7666 - Manual (Page 286)

9.5.2 Receive Overrun
Since the receive direction of the MAXQ7665/MAXQ7666 SPI is double buffered, there is no overrun condition as long as the received
character in the read buffer is read before the next character in the shift register is ready to be transferred to the read buffer. However,
if previous data in the read buffer has not been read out when a transfer cycle is completed and the new character is ready to be
loaded into the read buffer, a receive overrun occurs and the receive overrun flag (SPICN.5: ROVR) is set. Setting the ROVR flag indi-
cates that the most recent received character is lost. Setting the ROVR bit to logic 1 causes an interrupt if enabled. Once set, the ROVR
bit is cleared only by software or a reset.
9.5.3 Write Collision While Busy
A write collision occurs if an attempt to write the SPIB data buffer is made during a transfer cycle (STBY = 1). Since the shift register
is single buffered in the transmit direction, writes to SPIB are made directly into the shift register. Allowing the write to SPIB while anoth-
er transfer is in progress could easily corrupt the transmit/receive data. When such a write attempt is made, the current transfer con-
tinues undisturbed, the attempted write data is not transferred to the shift register, and the control unit sets the write collision flag
(SPICN.4:WCOL). Setting the WCOL bit to logic 1 causes an interrupt if SPI interrupt sources are enabled. Once set, the WCOL bit is
cleared only by software or a reset.
Normally, write collisions are associated solely with slave devices since they do not control initiation of transfers and do not have access
to as much information about SCLK as the master. As a master, write collisions are completely avoidable, however, the control unit
detects write collisions for both master and slave modes.
9.6 SPI Interrupts
Four flags in the SPI control register (SPICN) can generate an SPI interrupt when enabled.
• Mode Fault (MODF)
• Write Collision (WCOL)
• Receive Overrun (ROVR)
• SPI Transfer Complete (SPIC)
These four bits serve as interrupt flags that allow the system programmer to determine the source of interrupts that can cause an inter-
rupt request to the CPU. These bits default to 0 on a reset and must be cleared by software when set.
The ESPII bit in the SPI configuration register (SPICF) enables any of the SPI interrupt source flags (MODF, WCOL, ROVR, SPIC) to
generate interrupt requests. For interrupt requests to happen, global interrupt mask bits IM1 (in the IMR register) and IGE (in the IC
peripheral register) must also be enabled.
9.7 SPI Example: Enabling Master Mode
move SPICN, #03h ; Enable SPI for master mode communication
move SPICF, #00h ; Rising clock, active edge sample, 8-bit character
move SPICK, #0Fh ; Divide by 16 clock
MAXQ7665/MAXQ7666 User’s Guide
9-13
Maxim Integrated