Maxim Integrated MAXQ7666 - Manual (Page 16)

1.2.3.2 Utility ROM
A utility ROM (4k x 16) is placed in the upper 32kWord program memory space starting at address 8000h. This utility ROM provides
the following system utility functions:
• Reset vector
• Bootstrap function for system initialization
• In-application programming
• In-circuit debug
Following each reset, the processor automatically starts execution at address 8000h in the utility ROM, allowing ROM code to perform
any necessary system support functions. Next, the System Programming Enable (SPE) bit is examined to determine whether system
programming should commence or whether that code should be bypassed, instead forcing execution to vector to the start of user pro-
gram code. When the SPE bit is set to logic 1, the processor will execute the prescribed Bootstrap Loader mode program that resides
in utility ROM. The SPE bit defaults to 0. To enter the Bootstrap Loader mode, the SPE bit can be set to 1 during reset via the JTAG
interface. When in-system programming is complete, the Bootstrap Loader can clear the SPE bit and reset the device such that the in-
system programming routine is subsequently bypassed.
The MAXQ7665/MAXQ7666 application programming routines available as part of the utility ROM are covered in Sections 15 and 16.
The MAXQ7665/MAXQ7666 JTAG test access port, in-circuit debug, and bootstrap loader mode for in-system programming are cov-
ered in Sections 10, 11, and 12.
1.2.3.3 Data Memory
The MAXQ7665/MAXQ7666 contain 256 x 16 (512 bytes) of on-chip data SRAM that can be mapped into either program or data space.
The contents of this SRAM are indeterminate after power-on reset, but are maintained during stop mode and across non-POR resets,
as long as the DVDD supply stays within the acceptable range.
On-chip data memory begins at address 0000h and is contiguous through the internal data memory. Data memory is accessed via
indirect register addressing through a Data Pointer (@DP[n]) or Frame Pointer (@BP[OFFS]). The Data Pointer is used as one of the
operands in a MOVE instruction. If the Data Pointer is used as source, the core performs a Load operation that reads data from the
data memory location addressed by the Data Pointer. If the Data Pointer is used as destination, the core executes a Store operation
that writes data to the data memory location addressed by the Data Pointer. The Data Pointer can be directly accessed by the user
software.
The core incorporates two 16-bit Data Pointers (DP[0] and DP[1]) to support data memory accessing. All Data Pointers support indi-
rect addressing mode and indirect addressing with auto-increment or auto-decrement. Data Pointers DP[0] and DP[1] can be used as
post increment/decrement source pointers by a MOVE instruction or pre increment/decrement destination pointers by a MOVE instruc-
tion. Using Data Pointer indirectly with "++" will automatically increase the content of the active Data Pointer by 1 immediately follow-
ing the execution of read data transfer (@DP[n]++) or immediately preceding the execution of a write operation (@++DP[n]). Using
Data Pointer indirectly with "--" will decrease the content of the active Data Pointer by 1 immediately following the execution of read
data transfer (@DP[n]--) or immediately preceding the execution of a write operation (@--DP[n]).
The Frame Pointer (BP[OFFS]) is formed by 16-bit unsigned addition of Frame Pointer Base Register (BP) and Frame Pointer Offset
Register (OFFS). Frame Pointer can be used as a post increment/decrement source pointer by a MOVE instruction or as a pre incre-
ment/decrement destination pointer. Using Frame Pointer indirectly with "++" (@BP[++OFFS] for a write or @BP[OFFS++] for a read) will
automatically increase the content of the Frame Pointer Offset by 1 immediately before or after the execution of data transfer depending
upon whether it is used as a destination or source pointer respectively. Using Frame Pointer indirectly with "--" (@BP[--OFFS] for a write or
@BP[OFFS--] for a read) will decrease the content of the Frame Pointer Offset by 1 immediately before/after execution of data transfer
depending upon whether it is used as a destination or source pointer respectively. Note that the increment/decrement function affects the
content of the OFFS register only, while the contents of the BP register remain unaffected by the borrow/carry out from the OFFS register.
A data memory cycle contains only one system clock period to support fast internal execution. This allows read or write operations on
SRAM to be completed in one clock cycle. Data memory mapping and access control are handled by the MMU. Read/write access to
the data memory can be in word or in byte.
When using the in-circuit debugging features of the MAXQ7665/MAXQ7666, the top 19 bytes (bytes 0x1ED to 0x1FF) of the SRAM must
be reserved for saved state storage and working space for the debugging routines in the utility ROM. If in-circuit debug will not be
used, the entire SRAM is available for application use.
MAXQ7665/MAXQ7666 User’s Guide
1-14
Maxim Integrated