Maxim Integrated MAXQ7666 - Manual (Page 117)

MAXQ7665/MAXQ7666 User’s Guide
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3.3.8 ADC Clock
The MAXQ7665/MAXQ7666 ADC clock frequency is controlled by the ADCCD2:ADCCD0 bits in the OSCC control register and the sys-
tem clock speed. These bits determine the ADC clock frequency that is divided down from the system clock. Clock divide ratios of 1,
2, 4, 8, or 16 are supported. The MAXQ7665/MAXQ7666 ADC uses the divided system clock to clock the multiplexer front-end selec-
tion, track-and-hold acquisition, and each step of the successive approximation conversion. Note the system clock speed is deter-
mined by the divide ratio selected through the CD1 and CD0 bits in the CKCN register. By default, the CD1 and CD0 bits selected
divide ratio is 2 and the system clock speed is 3.8MHz if the internal RC oscillator is selected as the system clock source (XT = 0). The
ADCCD2:ADCCD0 bits selection further divides the system clock frequency to form the ADC clock.
The XT bit in the system clock control register, CKCN, selects the system clock source. If the XT bit is 0 (reset value), the internal RC
oscillator is configured as the system clock source. The internal RC oscillator runs at a nominal 7.6MHz frequency and is trimmed to
1% accuracy at room temperature. If the XT bit is set as 1, the external crystal/clock is configured as the system clock source. See
Section 5 for additional details on the system clock sources.
3.3.9 Auto Shutdown Mode
Power consumption is reduced significantly by placing the MAXQ7665/MAXQ7666 ADC in auto shutdown mode after a conversion.
Auto shutdown is ideal for infrequent data sampling and fast wake-up time applications. The ADCASD bit in the ACNT register con-
trols auto shutdown. If the ADCASD bit is set, the ADC automatically shuts down when a conversion is complete and the ADC data
ready (ADCRY) flag in the analog status register is set. If the ADCASD is not set, the ADC returns to acquisition mode after a conver-
sion. Auto shutdown reduces the ADC supply current (refer to the MAXQ7665/MAXQ7666 data sheet for exact current saving), but
there is a power-up delay of 10 ADC clock cycles (1.25µs at 8MHz) after an auto shutdown.
Note that auto shutdown is different from a full power-down state. The ADC is disabled and fully powered down if the ADCE bit in the
APE register is cleared. Full power-down reduces ADC supply current (refer to the MAXQ7665/MAXQ7666 data sheet for exact current
saving) and is ideal for infrequent data sampling. The ADCE bit is the master control for ADC operation and, unless set, no ADC con-
version is possible. From full power-down state (ADCE = 0), the ADC requires 10 ADC clock cycles (1.25µs at 8MHz) to power up.
Data in the ADC peripheral registers is not lost when the ADC is in auto shutdown or full power-down state. Setting the ADC auto shut-
down affects the PGA response. There is an additional delay of 40 cycles introduced in the PGA because of the ADC entering auto
shutdown state.
Figure 3-9. Analog Input Range Measuring a Negative Analog Input Value
REFADC
REFADC MAX INPUT = AVDD
AGND
AGND - 0.3V
AVDD
AVDD + 0.3V ABS MAX+
ABS MAX-
AIN-
AIN+
ADCIN = (AIN+ - AIN-) x PGA GAIN
REFADC MIN INPUT = 1V
DIFFERENTIAL
ANALOG
INPUT
DIFFERENTIAL INPUT
VOLTAGE RANGE
ABSOLUTE INPUT RANGE
(EITHER AIN+ OR AIN- PIN)
Maxim Integrated