Maxim Integrated MAXQ7666 - Manual (Page 265)

8.1.1 Port Pins
The MAXQ7665/MAXQ7666 port P0 pins are summarized in Table 8-1.
8.2 Port Registers
The following peripheral registers control the general-purpose I/O and external interrupt features specific to the MAXQ7665/MAXQ7666.
8.2.1 Port 0 Output Register (PO0)
Register Description: Port 0 Output Register
Register Name: PO0
Register Address: Module 00h, Index 00h
Bits 15 to 8: Reserved. Read returns 0, write ignored.
Bits 7 to 0: Port 0 Output Register Bits 7 to 0 (PO0.7 to PO0.0). Port 0 is a Type D I/O port. The PO0 register stores output data for
port 0 when it is defined as an output port and controls whether the internal pullup resistor is enabled/disabled if a port pin is defined
as an input. The contents of this register can be modified by a write access. Reading from the register returns the contents of the reg-
ister. Changing the direction of port 0 does not change the data contents of the register.
MAXQ7665/MAXQ7666 User’s Guide
8-3
r = read, w = write
Note: This register is cleared to FFh on all forms of reset.
Bit # 15 14 13 12 11 10 9 8
Name — — — — — — — —
Reset 0 0 0 0 0 0 0 0
Access r r r r r r r r
Bit # 7 6 5 4 3 2 1 0
Name PO0.7 PO0.6 PO0.5 PO0.4 PO0.3 PO0.2 PO0.1 PO0.0
Reset 1 1 1 1 1 1 1 1
Access rw rw rw rw rw rw rw rw
PIN NUMBER
PORT P0
SIGNALS
48-PIN 56-PIN
FUNCTION
P0.0/TDO 32 37
Port 0 Data 0/JTAG Serial Test Data Output. P0.0 is a general-purpose digital I/O with interrupt/wakeup
capability. TDO is the JTAG serial test data output. After power-up or a reset this pin defaults to JTAG TDO pin.
P0.1/TMS 33 38
Port 0 Data 1/JTAG Test Mode Select. P0.1 is a general-purpose digital I/O with interrupt/wakeup capability. TMS
is the JTAG test mode select input. After power-up or a reset this pin defaults to JTAG TMS pin.
P0.2/TDI 34 39
Port 0 Data 2/JTAG Test Data Input. P0.2 is a general-purpose digital I/O with interrupt/wakeup capability. TDI is
the JTAG serial test data input. After power-up or a reset this pin defaults to JTAG TDI pin.
P0.3/TCK 35 40
Port 0 Data 3/JTAG Test Clock Input. P0.3 is a general-purpose digital I/O with interrupt/wakeup capability. TCK
is the JTAG serial test clock input. After power-up or a reset this pin defaults to JTAG TCK pin.
P0.4/ADCCNV 36 41
Port 0 Data 4/ADC Conversion Start Input. P0.4 is a general-purpose digital I/O with interrupt/wakeup capability.
ADCCNV is the ADC conversion start input signal that can trigger ADC sampling and conversion on a rising or
falling edge. After power-up or a reset this pin defaults to a weakly pulled up general-purpose input.
P0.5/DACLOAD 37 43
Port 0 Data 5/DAC Load Input. P0.5 is a general-purpose digital I/O with interrupt/wakeup capability. DACLOAD
is the DAC load input signal that can trigger DAC conversion by loading the DAC output register on a rising or
falling edge. After power-up or a reset this pin defaults to a weakly pulled up general-purpose input.
P0.6/T0 24 27
Port 0 Data 6/Timer 0 Input/Output. P0.6 is a general-purpose digital I/O with interrupt/wakeup capability. As
Timer 0 Input/Output, the pin supports clock gating, capture/compare, counter, and PWM functionalities. After
power-up or a reset this pin defaults to a weakly pulled up general-purpose input.
P0.7/T1 25 29
Port 0 Data 7/Timer 1 Input/Output. P0.7 is a general-purpose digital I/O with interrupt/wakeup capability. As
Timer 1 Input/Output, the pin supports clock gating, capture/compare, counter, and PWM functionalities. After
power-up or a reset this pin defaults to a weakly pulled up general-purpose input.
Table 8-1. MAXQ7665/MAXQ7666 Port P0 Pins
Maxim Integrated