Maxim Integrated MAXQ7666 User Manual
Page 167
MAXQ7665/MAXQ7666 User’s Guide
4-37
4.2.4.11 CAN 0 Message Center 1 to 15 Control Registers (C0M1C to C0M15C)
Register Description:
CAN 0 Message Center 1 Control Register
Register Name:
C0M1C
Register Address:
Module 04h, Index 11h
Bits 15 to 8: Reserved. Read 0, write ignored.
Read/Write Access: MSRDY, ETI, ERI, and INTRQ are unrestricted read/write bits. EXTRQ is read/clear-only. When T/
R = 0, ROW is
read-only; when T/
R = 1, TIH is unrestricted read/write. MTRQ is unrestricted read and can only be set to 1 when written to by the micro-
controller or by the CAN controller in case of a remote frame reception in a transmit message center. A write of 0 to MTRQ leaves the
MTRQ bit unchanged. DTUP is unrestricted read. When T/
R = 0, DTUP can only be cleared to 0 when written by the microcontroller. A
write of 1 to DTUP with T/
R = 0 leaves the DTUP bit unchanged. DTUP is unrestricted read/write when T/R = 1.
Bit 7: CAN 0 Message Center 1 Ready (MSRDY). (Unrestricted read/write.) MSRDY is programmed by the microcontroller to notify
the CAN 0 logic when the associated message is ready for communication on the CAN 0 bus. When MSRDY = 0, the CAN 0 proces-
sor does not access this message center for either transmissions or to receive data or remote frame requests. MSRDY = 1 indicates
the message is ready for communication, and MSDRY = 0 indicates that the associated message is either not configured for use or is
not required at the present time. This bit is used by the microcontroller to prevent the CAN 0 logic from accessing a message while the
microcontroller is updating message attributes. These include identifiers (arbitration registers 0–3), data byte registers 0–7, data byte
count (DTBYC3, DTBYC0), direction control (T/
R), the extended or standard mode bit (EX/ST), and the mask enables (MEME and
MDME) associated with this message center. MSRDY is cleared to 0 following a microcontroller hardware reset or a reset generated
by the CRST bit in the CAN 0 control register, and must also remain in a cleared mode until all the CAN 0 initialization has been com-
pleted. Individual message MSRDY controls can be changed after initialization to reconfigure specific messages, without interrupting
the communication of other messages on the CAN 0 bus.
Bit 6: CAN 0 Message Center 1 Enable Transmit Interrupt (ETI). (Unrestricted read/write.) When ETI is cleared to 0, a successful
transmission does not set INTRQ and, as such, does not generate an interrupt. Setting ETI to 1 enables a successful CAN 0 trans-
mission to set the INTRQ bit, which in turn issues an interrupt to the microcontroller. Note that the CAN processor ignores the ETI bit
located in message center 15, since message center 15 is a receive-only message center.
Bit 5: CAN 0 Message Center 1 Enable Receive Interrupt (ERI). (Unrestricted read/write.) When ERI is cleared to 0, a successful
reception does not set INTRQ and, as such, does not generate an interrupt. When ERI is set to 1, the INTRQ bit only sets when the
CAN processor successfully receives and stores the incoming message into one of the message centers. Setting INTRQ, in turn, issues
an interrupt request to the microcontroller.
Bit 4: Interrupt Request (INTRQ). (Unrestricted read/write.) INTRQ is automatically set to 1 by the CAN 0 logic when the ERI is set
and the CAN 0 logic completes a successful reception and store. The INTRQ bit is also set to 1 when the ETI is set and the CAN 0
logic completes a successful transmission. The INTRQ interrupt request must be also enabled via the IGE global mask in the IC periph-
eral register and the IM4 mask in the IMR peripheral register, if the interrupt is to be acknowledged by the microcontroller interrupt
logic. An active message center interrupt is cleared by writing a 0 to the INTRQ bit in the respective CAN message control register.
Bit #
15
14
13
12
11
10
9
8
Name
— — — — — — — —
Reset
0 0 0 0 0 0 0 0
Access
r
r
r
r
r
r
r
r
Bit #
7
6
5
4
3
2
1
0
Name MSRDY
ETI
ERI
INTRQ
EXTRQ
MTRQ
ROW/TIH
DTUP
Reset
0 0 0 0 0 0 0 0
Access rw
rw
rw
rw
rc
r*
r*
r*
r = read, w = write, c = clear only, * = see description
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