Maxim Integrated MAXQ7666 - Manual (Page 153)

MAXQ7665/MAXQ7666 User’s Guide
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Bit 4: Low-Power Siesta Mode (SIESTA). Setting the SIESTA bit to 1 places the CAN 0 controller into a low-power static state after
completion of the last reception, transmission, or after the arbitration was lost or an error condition occurred. Note that the term "after
arbitration lost" denotes the fact the arbitration was lost and the reception following this lost arbitration is completed. Recall that the
CAN processor immediately becomes a receiver after it has lost its arbitration on the CAN bus. Programming SIESTA = 0 disables the
low-power mode. The state of when the SIESTA mode is actually enabled or removed, as per the SIESTA bit programmed value, is
reflected in the read of the SIESTA bit. The SIESTA mode is removed when the CAN 0 controller detects CAN 0 bus activity, by repro-
gramming the SIESTA bit to 0, or by setting either CRST or SWINT to 1. When the SIESTA bit is cleared by either a microcontroller write
or activity on the CAN 0 bus, the CAN controller begins operation after 11 recessive bits on the CAN bus (after a power-up sequence)
using the configuration settings that were programmed prior to entering the power-down mode. Changing the SIESTA bit from 0 to 1
does not disrupt a currently active receive or transmit, but allows the completion of CAN 0 bus activity prior to entering into the static
state. If the CAN 0 logic issues an interrupt as a result of an active CAN 0 receive or transmit while SIESTA is being set, the SIESTA bit
is cleared and the CAN 0 logic does not enter the low-power mode. Since WKS reflects when the CAN has entered the low-power state
as per the SIESTA and/or PDE bit states, a read of the SIESTA bit establishes when the SIESTA bit is actually allowed to enable the low-
power state. If the low-power state was previously enabled by setting the PDE bit, a read of SIESTA reflects the actual SIESTA bit value
and not the low-power mode. If the low-power mode has not been previously enabled and the SIESTA bit is set to 1 by software, a read
of SIESTA returns a 0 until such time that the SIESTA bit actually enables the low-power mode following an active transmit or receive
operation. When the PDE and SIESTA bit are not used together, a read of the SIESTA bit, by default, also reflects the actual state of the
low-power mode. Setting SIESTA does not alter any CAN block controls or error status relationships. Note that the PDE and SIESTA bits
act independently of each other. Setting both bits leaves the CAN processor in a low-power state until both bits have been cleared by
their respective mechanisms.
Bit 3: CAN 0 Reset (CRST). When CRST is set to 1 and after completion of the last reception, transmission, or after arbitration was lost
or an error condition occurred, all CAN registers located in the peripheral register memory map, with the exception of the CAN 0 con-
trol register, are cleared to 00h. The CAN 0 control register is set to 09h. Note that the term "after arbitration lost" denotes the fact that
the arbitration was lost and the reception following this lost arbitration is completed. Recall that the CAN processor immediately becomes
a receiver after it has lost its arbitration on the CAN bus. In accordance with waiting until after the completion of the last reception, trans-
mission, or after arbitration was lost or an error condition occurred, a read of the CRST bit, when previously programmed to 1, reads as
a 0 until such time that the CRST = 1 state is actually allowed to place the CAN processor into the reset state. As such, a read of the
CRST bit verifies when the CAN reset has been engaged or removed. CAN registers located in the dual port memory map are left in the
last state prior to setting CRST. Setting CRST also clears both the receive- and transmit-error counters in the CAN controllers and sets
the SWINT bit to 1. CRST must be cleared by software to remove the CAN reset and allow the CAN 0 processor to be initialized. When
the CAN processor is not in a BUSOFF mode (BSS = 0) and the CAN processor exits either the software initialization mode (SWINT pro-
grammed from 1 to 0) or when the CAN reset is removed (CRST bit is cleared from 1 to 0 and the SWINT bit is cleared from 1 to 0), the
CAN processor performs a power-up sequence of 11 consecutive recessive bits before the CAN controller enters into normal operation.
If the CAN reset is removed and SWINT is left in the software initialization state, the microcontroller is allowed to immediately start pro-
gramming the CAN registers and dual port data memory prior to the completion of the power-up sequence. Exiting the software initial-
ization mode (SWINT
≥ 0) requires a power-up sequence of 11 consecutive recessive bits before the CAN controller enters into normal
operation. Clearing CRST to 0 from a previous 0 state does not alter CAN processor operation.
Bit 2: Autobaud (AUTOB). When AUTOB is set to 1, an internal loop back is enabled to AND the data from the external CAN bus with
the transmitted data of the CAN 0 processor. The ANDed data is then connected to the internal input of the CAN 0 processor. At the
same time, the transmitted data is disabled from reaching the external CANTXD pin. The CANTXD pin is placed into a recessive state
when AUTOB = 1. The purpose of the internal loopback and the disabled CANTXD pin is to allow the CAN processor to establish the
proper CAN bus timing without disrupting the normal data flow between other nodes on the CAN bus. Disabling the CANTXD pin and
setting the CANTXD pin to a recessive state prevents the CAN processor from driving nonsynchronized data onto the CAN bus (cre-
ating CAN bus errors to other nodes) when being programmed with various frequencies to synchronize the processor with the CAN
bus. With AUTOB = 1, the microcontroller autobaud algorithm makes use of the CAN 0 status register RXS and error status bits to deter-
mine when a message is successfully received (when AUTOB =1, a successful receive, does not require a store). Each successive
baud rate attempt is preceded by the microcontroller clearing the transmit- and receive-error counters by means of a write of 00 to the
transmit-error peripheral register and a read of the CAN 0 status register to clear the previous status change interrupt. Note that a write
to the transmit-error peripheral register automatically resets the CAN fault confinement state machine to an initial (error active) state if
the error counters are cleared to 00h. If, however, the error counters are programmed to a value greater than 128, the CAN processor
is in an error-passive state. Appropriate flags are set when the error counter is written with any value. A write of the status register is
also used to remove the previous error value in the ER2:ER0 bits. Clearing the error counters also clears the EC96 bit, if set. When BSS
= 1, the CAN processor locks out the ability for the microcontroller to write to the error counters by virtue of the fact that the SWINT bit
is also forced to a 0 state during the period that the CAN processor performs a bus recovery and power-up sequence. Once the CAN
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