Maxim Integrated MAXQ7666 - Manual (Page 225)

6.2.2 Serial Port 0 Mode Register (SMD0)
Register Description: Serial Port 0 Mode Register
Register Name: SMD0
Register Address: Module 00h, Index 1Eh
Bits 15 to 3: Reserved.
Bit 2: Enable Serial Port Interrupt (ESI). Setting this bit to 1 enables interrupt requests generated by the RI or TI flags in SCON0.
Clearing this bit to 0 disables the serial port interrupt. Note: For interrupt requests to happen, global interrupt mask bits IM0 (in the IMR
register) and IGE (in the IC peripheral register) must also be enabled.
Bit 1: Serial Port Baud Rate Select (SMOD). The SMOD bit selects the final baud rate for the asynchronous mode:
SMOD = 1: 16 times the baud clock for modes 1 and 3 (32 times the system clock for mode 2).
SMOD = 0: 64 times the baud clock for modes 1 and 3 (64 times the system clock for mode 2).
Bit 0: Framing Error Detection Enable (FEDE). This bit selects the function of the SM0/FE (SCON0.7) bit. Note: The information for
bits SM0 and FE are actually stored in different registers. Changing FEDE only modifies which register is accessed, not the contents
of either.
FEDE = 0: SM0/FE bit functions as SM0 for serial port mode selection.
FEDE = 1: SM0/FE is converted to the framing error (FE) flag.
MAXQ7665/MAXQ7666 User’s Guide
6-7
r = read, w = write
Bit # 15 14 13 12 11 10 9 8
Name — — — — — — — —
Reset 0 0 0 0 0 0 0 0
Access r r r r r r r r
Bit # 7 6 5 4 3 2 1 0
Name — — — — — ESI SMOD FEDE
Reset 0 0 0 0 0 0 0 0
Access r r r r r rw rw rw
Maxim Integrated