Maxim Integrated MAXQ7666 - Manual (Page 308)

11.3.2 Breakpoint Registers
The MAXQ7665/MAXQ7666 incorporate six host-configurable breakpoint registers (BP0–BP5) for establishing different types of break-
point mechanisms. The first four breakpoint registers (BP0–BP3) are 16-bit registers that are configurable as program memory address
breakpoints. When enabled, the debug engine forces a break when a match between the breakpoint register and the program mem-
ory execution address occurs. The final two 16-bit breakpoint registers (BP4 and BP5) are configurable in one of two ways. They can
be configured as data memory address breakpoints or can be configured to support register-access breakpoints. In either case, if
breakpoints are enabled and the defined breakpoint match occurs, the debug engine generates a break condition. The six breakpoint
registers are detailed in the following sections.
11.3.2.1 Breakpoint Registers 0 to 3 (BP0 to BP3)
The BP0 to BP3 registers are accessible only via background mode read/write debug commands. These four registers serve as pro-
gram memory address breakpoints. When the DME bit is set, the debug engine monitors the program address bus activity while the
CPU is executing the user program. A break occurs when the address pattern matches with the contents of these registers, allowing
the debug engine to take control of the CPU and enter debug mode.
Register Description: Breakpoint Register x (where x = 0, 1, 2, 3)
Register Name: BPx
Bits 15 to 0: Breakpoint Register x Bits 15 to 0 (BPx.15 to BPx.0). These registers default to FFFFh after a power-on reset or test-
logic-reset TAP state.
MAXQ7665/MAXQ7666 User’s Guide
11-12
Bit # 15 14 13 12 11 10 9 8
Name BPx.15 BPx.14 BPx.13 BPx.12 BPx.11 BPx.10 BPx.9 BPx.8
Reset 1 1 1 1 1 1 1 1
Access s s s s s s s s
Bit # 7 6 5 4 3 2 1 0
Name BPx.7 BPx.6 BPx.5 BPx.4 BPx.3 BPx.2 BPx.1 BPx.0
Reset 1 1 1 1 1 1 1 1
Access s s s s s s s s
s = special (accessible only by background mode read/write commands)
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