Maxim Integrated MAXQ7666 - Manual (Page 216)

Table 5-4. Interrupt and Reset Functions for Watchdog
Table 5-5. Watchdog Timeout Selections
The watchdog timeout selection is made using bits WD1 (WDCN.5) and WD0 (WDCN.4). The watchdog has four timeout selections
based on the internal RC clock as shown in Table 5-5.
Using the watchdog interrupt during software development can allow the user to select ideal watchdog reset locations. Code is first
developed without enabling the watchdog interrupt or reset functions. Once the program is complete, the watchdog interrupt function
is enabled to identify the required locations in code to set the RWT (WDCN.0) bit. Incrementally adding instructions to refresh the watch-
dog timer prior to each address location (identified by the watchdog interrupt) allows the code to eventually run without receiving a
watchdog interrupt. At this point, the watchdog timer reset can be enabled without the potential of generating unwanted resets. At the
same time the watchdog interrupt may also be disabled. Proper use of the watchdog interrupt and watchdog reset allows interrupt soft-
ware to survey the system for errant conditions.
When using the watchdog timer as a system monitor, the watchdog reset function should be used. If the interrupt function were used,
the purpose of the watchdog would be defeated. For example, assume the system is executing errant code prior to the watch dog
interrupt. The interrupt would temporarily force the system back into control by vectoring the CPU to the interrupt service routine.
Restarting the watchdog and exiting by an RETI or RET, would return the processor to the lost position prior to the interrupt. By using
the watchdog reset function; the processor is restarted from the beginning of the program, and therefore placed into a known state.
RCE EWT EWDI WDIF OPERATION
0 x x x Watchdog disabled.
1 0 0 x Watchdog disable, clock is gated off.
1 0 1 0 Watchdog interrupt is enabled and has not occurred. Watchdog reset function disabled.
1 0 1 1 Watchdog interrupt is enabled and has occurred. Watchdog reset function disabled.
1 1 0 0 Watchdog reset function is enabled. Watchdog interrupt is disabled.
1 1 0 1
Watchdog reset function is enabled. No interrupt has been generated. Watchdog reset will occur in
512 RC cycles if RWT is not set.
1 1 1 0 Watchdog reset and interrupt functions are enabled.
1 1 1 1
Watchdog reset and interrupt functions are enabled. Watchdog interrupt has occurred. Watchdog
reset will occur in 512 RC cycles if RWT is not set.
WATCHDOG TIMEOUT PERIOD
RC CLOCKS MILLISECONDS (FOR RC = 7.6MHz) WD1 WD0
UNTIL INTERRUPT UNTIL RESET UNTIL INTERRUPT UNTIL RESET
0 0 2 12 (default) 2 12 + 2 9 0.539 0.606
0 1 2 15 2 15 + 2 9 4.31 4.38
1 0 2 18 2 18 + 2 9 34.49 34.56
1 1 2 21 2 21 + 2 9 275.94 276
MAXQ7665/MAXQ7666 User’s Guide
5-19
Maxim Integrated