Maxim Integrated MAXQ7666 - Manual (Page 217)

MAXQ7665/MAXQ7666 User’s Guide
5-20
5.5 Power Management Mode
There are two major sources of power dissipation in CMOS circuitry. The first is static dissipation caused by leakage current. The sec-
ond is dynamic dissipation caused by transient switching current required to charge and discharge load capacitors, as well as short-
circuit current dissipated by momentary connections between V
DD and ground during gate switching.
Usually, it is the dynamic switching power dissipation that dominates the total power consumption, and this power dissipation (P D ) for
a CMOS circuit can be calculated in terms of load capacitance (C L ), power-supply voltage (V DD ), and operating frequency (f) as
P D = C L x V DD2 x f
Capacitance and supply voltage are technology dependent and relatively fixed. However, the operating frequency determines the
clock rate, and the required clock rate may be different from application to application depending on the amount of processing power
required. If an external crystal or oscillator is being used, the operating frequency can be adjusted by changing external components.
However, it may be the case that a single application may require maximum power at sometimes and very little at others. Power man-
agement mode allows an application to reduce its clock frequency, and therefore its power consumption, under software control.
The MAXQ7665/MAXQ7666 provide the following features to assist in power management:
• Divide-by-256 (PMM) mode to reduce current consumption.
• Switchback mode to exit PMM automatically when rapid processing is required.
• Ultra-low-power stop mode.
Table 5-6 shows the system clock control register (CKCN) bits used to control power management features.
Table 5-6. System Power Management
5.5.1 Divide-by-256 Mode (PMM)
In this power management mode, all operations continue as normal but at a reduced clock rate (the selected clock source divided by
256). This power management mode affects module clock rates as follows:
• Program execution occurs at the selected clock source rate divided by 256.
• All other functional modules (CAN, ADC, timers, UART, and SPI) operate at the selected clock source rate divided by 256.
• Watchdog timer, if enabled, continues to operate using the internal, undivided 7.6MHz RC oscillator as the clock source.
The power management mode is entered by setting the PMME bit (CKCN.2) to 1 while the CD1 and CD0 (CKCN1:CKCN0) bits are
both cleared to 0. When PMM mode is exited (either by clearing the PMME bit or as a result of a switchback trigger), system opera-
tion will revert to the mode indicated by the values of the CD1 and CD0 bits, which in this case will be the standard divide-by-1 clock
mode.
Note: The CD1 and CD0 (CKCN1:CKCN0) bits must both be cleared to 0 before setting the PMME bit to 1.
REGISTER ADDRESS BIT NAME FUNCTION
1:0 CD[1:0]
Selects clock divide-by-1 (00), -2 (01), -4 (10), or -8 (11) mode. When PMM mode is enabled,
selects divide-by-256 (00) mode.
2 PMME Selects PMM mode (when set to 1) or normal clock divide mode (when set to 0)
3 SWB
When set to 1, enables automatic switchback from PMM (divide-by-256 mode) to normal clock
divide mode under certain conditions.
CKCN M8[0Eh]
4 STOP When set to 1, causes the processor to enter stop mode.
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